Low power, minimal area tap multiplier

Details Low power, minimal area tap multiplier Low power, minimal area tap multiplier

2005-12-27

2005-12-27

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

06981013

ABSTRACT:
A low power tap multiplier multiplies a m-bit multiplier and a n-bit multiplicand to output a p-bit multiplication product. The p-bit product is one bit more than the n-bit multiplicand when the multiplicand is symmetric, and two bits more when the multiplicand is non-symmetric. Since the low power tap multiplier utilizes a minimal number of small unstacked transistors, it consumes less power and requires less silicon area.

REFERENCES:
patent: 4941121 (1990-07-01), Zurawski
patent: 5126964 (1992-06-01), Zurawski
patent: 5231601 (1993-07-01), Stearns
patent: 5442579 (1995-08-01), Thomson
patent: 6684236 (2004-01-01), Farnbach

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