Low power memory sub-system architecture

Details Low power memory sub-system architecture Low power memory sub-system architecture

2007-04-24

2007-04-24

Phung, Anh (Department: 2824)

Static information storage and retrieval

Powering

C365S227000

Reexamination Certificate

active

11198563

ABSTRACT:
Disclosed methods and apparatus provide embedded memory architectures that lower the overall operational power consumption of memory arrays without sacrificing memory access speed. Because in large memory arrays the leakage current is a considerable portion of the overall power consumption, leakage reduction in memory arrays, manufactured by advanced processing technologies, is a major challenge. To reduce leakage, methods and apparatus are presented for memory access and for power- and ground-supply monitoring and management at memory sub-array level.

REFERENCES:
patent: 5808500 (1998-09-01), Kalpakjian
patent: 6141283 (2000-10-01), Bogin et al.
patent: 6330180 (2001-12-01), Noro et al.
patent: 6552949 (2003-04-01), Silla et al.
patent: 6917555 (2005-07-01), Bedwell et al.

Affiliated with

Also associated with

Rating

Low power memory sub-system architecture does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power memory sub-system architecture, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power memory sub-system architecture will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3781449