Low-power memory device with accelerated sense amplifiers

Details Low-power memory device with accelerated sense amplifiers Low-power memory device with accelerated sense amplifiers

1994-09-23

1996-06-11

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

365205, 365227, G11C 1300, G11C 700

Patent

active

055263224

ABSTRACT:
An AND array for an erasable programmable logic device (EPLD) includes word-line transition detectors for indicating high-to-low word-line transitions. Such transitions are a condition precedent for low to-high bit line transitions. Transition indications are buffered by a fast transition-detection sense amplifier, the output of which is provided to each of plural "mode-switchable" sense amplifiers that read out the bit lines for the AND array. Each mode-switchable sense amplifier logically combines the transition indication with its own output to select its operating mode. A fast (strong source-current) mode is entered only when,the transition indication is active and the present output of the sense amplifier is low. Otherwise, which is most of the time, the mode switchable sense amplifier remains in a low-power (weak source-current) mode. This arrangement provides higher speed operation with relatively low time-averaged power consumption.

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