Low-power, low-jitter, fractional-N all-digital phase-locked...

Details Low-power, low-jitter, fractional-N all-digital phase-locked... Low-power, low-jitter, fractional-N all-digital phase-locked...

2008-04-29

2008-04-29

Pascal, Robert J. (Department: 2817)

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

C331S017000, C327S156000, C375S376000

Reexamination Certificate

active

11463630

ABSTRACT:
A method for synthesizing frequencies with a low-jitter an all-digital fractional-N phase-locked loop (PLL) electronic circuit adapted to synthesize frequencies with low-jitter, wherein the electronic circuit comprises a digital phase-frequency detector (DPFD) operatively connected to a digital loop filter (DLF), wherein the DPFD adapted to receive a reference signal and a feedback signal; compare a phase and frequency of the reference and feedback signals to determine a phase and frequency error between the reference and feedback signals; and provide a DPFD output comprising a multi-bit output; wherein the DLF is adapted to receive and filter the DPFD output and provide a DLF output, and wherein the DLF output is updated at each reference period.

REFERENCES:
patent: 6504498 (2003-01-01), O'Brien
patent: 6784755 (2004-08-01), Lin et al.
patent: 7282999 (2007-10-01), Da Dalt et al.
patent: 2005/0206458 (2005-09-01), Wu
patent: 2006/0017512 (2006-01-01), Huang

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