Low power, low interconnect complexity microprocessor and memory

Details Low power, low interconnect complexity microprocessor and memory Low power, low interconnect complexity microprocessor and memory

1997-06-02

1999-03-30

Hua, Ly V.

Electrical pulse counters, pulse dividers, or shift registers: c

Counting or dividing in incremental steps

Beam type tube

377 41, 711102, H03K 19003

Patent

active

058900055

ABSTRACT:
A method is disclosed for reducing the power consumption of an electronic system, such as a wireless or cellular telephone, that has a memory and a device for accessing the memory. The method includes the steps of (a)during a first part of a memory access cycle, applying an address over a bus; (b) during a second part of the memory access cycle, transferring data to or from the memory over at least a portion of the bus; and (c) prior to the step of transferring, selectively inverting or not inverting the data so as to minimize a number of bus signal lines that are required to change state between the first part and the second part of the memory access cycle. In a preferred embodiment of the invention the bus is a multiplexed address/data bus. The method also generates a control signal that is transmitted to the bus for informing a receiving device that the data (or address) being transferred over the multiplexed address/data bus should be inverted before use. Also disclosed is a memory that operates in a burst mode by incrementing or decrementing memory addresses using a clock signal, and that operates with the power saving circuitry to selectively invert or not invert burst mode data read from or written to the memory.

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MOS Memory Data Book 1984, Commercial and Military Specifications, Texas Instruments, pp. 9-1--9-61 "TMS4500A Dram Controller Configured For The TMS99000 Series 16-Bit Microprocessors-- and pp. 9-63--9-68 TMS4500A/8088 Interface".

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