Low power logic minimization for electrical circuits

Details Low power logic minimization for electrical circuits Low power logic minimization for electrical circuits

1995-10-26

1998-05-05

Teska, Kevin J.

Boots, shoes, and leggings

G06F 1750

Patent

active

057484902

ABSTRACT:
A process (601-611) and implementing computer system (13) for selecting a specific logic circuit among a group of otherwise acceptable alternative circuits, as represented by prime implicant terms (607), includes determining and assigning a power consumption factor (609) to each of the alternative logic circuit implementations. In the disclosed example, the probability of switching logic states (313, 513) is determined and used as a measure of the power consumption factor associated with each of the acceptable and valid prime implicant solutions for a given logic function. From a group of acceptable prime implicant solutions, the power optimum solution is chosen (611) which has been determined to be the most likely to consume the least amount of power in implementing the desired logic function.

REFERENCES:
patent: 5434794 (1995-07-01), Coudert et al.
patent: 5452215 (1995-09-01), Washabaugh
patent: 5502648 (1996-03-01), Kaplan
Charles H. Roth, Jr., "Fundamentals Of Logic Design", Section 6.1 Minimum Forms of Switching Functions, Published in 1992 by West Publishing Co., pp. 116-131.
Charles H. Roth, Jr., "Fundamentals Of Logic Design", Section 7.1 Determination of Prime Implicants, Published in 1992 by West Publishing Co., pp. 155-161.
Ashar et al., "Optimium & Huristic Algorithms for an Approach to Finite State Machine Decomposition," IEEE Trans. on CAD, vol. 10, No. 3, Mar. 1991, pp. 296-310.
Benini et al., "State Assignment for Low Power Dissipation," IEEE J. of Solid State Circuits, vol. 30, No. 3, Mar. 1995, pp. 258-268.
Devadas et al., "Exact Algorithms for Output Encoding, State Assignment, and Four-Level Boolean Minimization," IEEE Trans. on CAD, vol. 10, No. 1, Jan '91, pp. 13-27.
Helstrom, Probability and Stochastic Processes for Engineers, 1991, pp. 35-39, Macmillan Publishing Company.
Iman et al., "Two-Level Logic Minimization for Low Power," ICCAD '95, pp. 433-438.
Perkowski et al., "KUAI-EXACT: A New Approach for Multi-Valued Logic Minimization in VLSI Synthesis," ISCAS '89, pp. 401-404.
Roy et al., "SYCLOP: Synthesis of CMOS Logic for Low Power Applications," ICCD '92, pp. 464-467.
Tsui et al., "Power Estimation Methods for Sequential Logic Circuits," IEEE Trans. on VLSI Systems, vol. 3, No. 3, Sep. 1995, pp. 404-416.
Yang et al., "Estimating Power Dissipation in VLSI Circuits," Circuits and Devices, Jul. 1994, pp. 11-19.

Affiliated with

Also associated with

Rating

Low power logic minimization for electrical circuits does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power logic minimization for electrical circuits, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power logic minimization for electrical circuits will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-61884