Low power linear feedback shift registers

Details Low power linear feedback shift registers Low power linear feedback shift registers

1999-05-13

2002-08-27

Malzahn, David H. (Department: 2124)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

C377S072000, C377S078000

Reexamination Certificate

active

06442579

ABSTRACT:

The present invention relates to shift registers and more particularly to low power linear feedback shift registers.
BACKGROUND
Linear feedback shift registers (LFSR) are used in many different electronic apparatuses such as computers, calculators, personal organisers mobile phones etc.
A register is normally used as a storage for a set of information, usually a binary word. Conventionally, an n-bit register is an ordered set of n flip-flops used to store an n-bit word. Each bit of the word is stored in a separate flip-flop. Registers where the words or data transferred to or from the register in parallel are usually designed with D latches or D flip-flops. A widely used register design organized to allow left- or right-shift operations of the stored information is called a shift register. An n-bit shift register may consist of n D flip-flops each of which is connected to its left and/or right neighbour. Data may be entered 1 bit at a time at one end of the register and may be read 1 bit at a time from the other end, which is called serial input-output. A right shift of a D flip-flop shift register is achieved by enabling the clock input of each flip-flop.
A problem with the above mentioned prior art shift register designs is that when they are used in applications or apparatuses, such as mobile phones, where power consumption is critical, the power consumption in the flip-flops in the shift registers is a considerable portion of the total power consumption in the current apparatus.
However, U.S. Pat. No. 5,295,174 discloses a shifting circuit having lower power consumption and a shift register employing the same. The shift register comprises a plurality of latch circuits, a multiplexer for selecting outputs of the latch circuits in sequence, and a clock control circuit for generating clocks used for controlling selection timings of the multiplexer, wherein the timing for selecting the output of a certain latch circuit is delayed with respect to the latch timing of the certain latch circuit by a predetermined timing.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an improved linear feedback shift register (LFSR) reducing the power consumption problem.
This is accomplished by a low power linear feedback shift register according to the invention, using memory means such as flip-flops not consuming power when they are disabled. The register does not shift any bits but still generates the same sequence as a conventional linear feedback shift register.
The register comprises enabling means enabling a single current memory means at every shift operation, register steps, each comprising a low power memory means consuming a minimum of power when it is disabled, and feedback means of each step. Each memory means is connected to selection means, selecting at every shift operation the output terminal of a first subsequent memory means following the current memory means being enabled at the current shift operation.
Another object of the present invention is to provide said enabling means.
Still another object of the invention is to provide said selection means.
An advantage of the low power linear feedback shift register according to the invention is the reduction in power consumption.


REFERENCES:
patent: 5090035 (1992-02-01), Murase
patent: 5295174 (1994-03-01), Shimizu
patent: 5867409 (1999-02-01), Nozuyama
patent: 5974433 (1999-10-01), Currie
patent: 6014408 (2000-01-01), Naruse et al.

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