Low power level converter

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

307443, 307446, H03K 19094

Patent

active

052025942

ABSTRACT:
A low power level converter (20), for converting from one logic level to another, includes six transistors (21 through 26). Two transistors (23 and 25) are connected to form a current mirror. A power supply voltage is provided to both sides of the current mirror through a third and a fourth transistor (22 and 26). The third and fourth transistors receive complementary signals V.sub.I and V.sub.I. A fifth transistor (21) is connected between the third transistor and the power supply, and a sixth transistor (24) is connected across the current mirror. An output signal, provided at the mirror side of the current mirror, is fed back into the converter at the control electrodes of the fifth and sixth transistors and utilized to prevent a constant undesirable DC current from flowing between the power supply voltage terminals, thereby reducing the power consumption of the converter. One embodiment uses P-channel and N-channel transistors.

REFERENCES:
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patent: 4906871 (1990-03-01), Iida
patent: 4961011 (1990-10-01), Ide et al.
patent: 4968905 (1990-11-01), Sanwo et al.
patent: 4992681 (1991-02-01), Urakawa et al.
patent: 4996443 (1991-02-01), Tateno
patent: 5012137 (1991-04-01), Muellner
patent: 5047657 (1991-09-01), Seevinck et al.
patent: 5068551 (1991-11-01), Bosnyak
patent: 5148059 (1992-09-01), Chen et al.
Robert A. Kertis, "A 12ns 256K BiCMOS SRAM", ISSCC 88, Feb. 18, 1988, FIG. 2, p. 187.

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