Low power latch sense amplifier

Details Low power latch sense amplifier Low power latch sense amplifier

2002-09-30

2004-04-06

Nuton, My-Trang (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

Reexamination Certificate

active

06717444

ABSTRACT:

This application incorporates by reference of Taiwan application Serial No. 091100272, filed on Jan. 10, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a low power latch sense amplifier, and more particularly to a low power latch sense amplifier used in a memory device.
2. Description of the Related Art
Non-volatile semiconductor memory is frequently used in many information technology products. Therefore, the need of greater memory capacity of a non-volatile semiconductor memory device increases as the technology grows.
The non-volatile semiconductor memory device includes a memory cell array. Each memory cell stores data of 1 or 0. The memory cell can be implemented by a metal-oxide semiconductor (MOS) with different threshold voltage according to the data to be stored. Bit lines are used for selecting one column of memory cells, and word lines are used for selecting one row of memory cells. Then, a selected memory cell is read under the control of a selected bit line and a selected word line, and the corresponding current signal of the bit line is transmitted to a sense amplifier to output a voltage signal corresponding to the current signal.
For a memory device having a great number of sense amplifiers operating at the same time, power consumption increases instantly. Therefore, reducing the power consumption of the sense amplifiers is an important topic for the persons skilled in the arts.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a low power latch sense amplifier to reduce the number of MOS and to lower the power consumption. Also, the swing of the bit line is decreased and the reliability of the memory cell array is increased because the voltage of the bit lines is clamped at a fixed voltage value in the invention.
It is another object of the invention to provide a low power latch sense amplifier for being electrically coupled to a bit line of a memory cell array. The low power latch sense amplifier comprises a common gate sense amplifier and an activated latch register. The common gate sense amplifier, which comprises a current source and a biased metal-oxide semiconductor, is applied for sensing the current of the bit line. The current source and the biased MOS are coupled to a first node, and the common gate sense amplifier outputs a sensing signal at the first node. The activated latch register comprises a first clock signal-synchronized inverter which includes a first inverter and a first switch. The first inverter outputs a first inverter output signal in response to the sensing signal. The first switch is controlled by a first set of control signal. The first inverter output signal corresponds to the sensing signal when the first switch is turned on. The latch sense amplifier takes the first inverter output signal as its output.
Other objects, features, and advantages of the invention will become apparent from the following detailed description of the preferred but non-limiting embodiments. The following description is made with reference to the accompanying drawings.


REFERENCES:
patent: 4434381 (1984-02-01), Stewart
patent: 5486779 (1996-01-01), Eitrheim
patent: 5740112 (1998-04-01), Tanaka et al.
patent: 6438051 (2002-08-01), Fifield et al.
patent: 6535026 (2003-03-01), Chung et al.

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