Low power latch requiring reduced circuit area

Details Low power latch requiring reduced circuit area Low power latch requiring reduced circuit area

1997-06-24

1998-12-29

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, 327211, H03K 3289

Patent

active

058545654

ABSTRACT:
The present invention is a novel and improved method and apparatus for implementing a latch within an integrated circuit. Data is stored on a storage node via the application of either a first or second state logic source applied through a feedback inverter that maintains the storage node at a particular logic state. During logic transitions from a first state to a second state the storage node is decoupled from the first state logic source via the use of a gating circuit, and the new logic level is applied to the storage node. During logic transitions from the second state to the first state the storage node remains coupled to the second state logic source. The coupling and decoupling of the storage node from the first state logic source is performed via the use of a clock signal that has a non-overlapping cycle with respect to a second clock signal that is used to control the transitions of the state of the latch.

REFERENCES:
patent: 4495629 (1985-01-01), Zasio et al.
patent: 4554467 (1985-11-01), Vaughn
patent: 5015875 (1991-05-01), Giles et al.
patent: 5130568 (1992-07-01), Miller et al.
patent: 5175447 (1992-12-01), Kawasaki et al.
patent: 5444404 (1995-08-01), Ebzery
patent: 5461331 (1995-10-01), Schorn

Affiliated with

Also associated with

Rating

Low power latch requiring reduced circuit area does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power latch requiring reduced circuit area, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power latch requiring reduced circuit area will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1427188