Low-power, jitter-compensated phase locked loop and method there

Details Low-power, jitter-compensated phase locked loop and method there Low-power, jitter-compensated phase locked loop and method there

1993-07-28

1994-12-13

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

331 17, 331 25, 331 27, 327 7, 327159, H03L 7089, H03L 7091, H03L 7093

Patent

active

053732553

ABSTRACT:
A phase locked loop (PLL) (40) simultaneously has both relatively-low power consumption and relatively-low jitter on a clock output signal. The PLL (40) includes a phase detector (41) and a phase error accumulator (42) connected to the output of the phase detector (41). The phase error accumulator (42) samples an output of the phase detector (41) at a relatively-high clock rate, but accumulates these samples and provides an output thereof to a loop filter (43) at a relatively-low clock rate. Thus the PLL (40) captures short periods of phase delay to maintain low clock output signal jitter, while at the same time, however, the loop filter (43) need only adjust its output periodically, at the relatively-low rate, thereby saving power. The phase detector (41) detects a metastable condition on a phase detector latch (60) and resolves to an up pulse or a down pulse to further reduce clock output signal jitter.

REFERENCES:
patent: 3989931 (1976-11-01), Phillips
patent: 4378509 (1983-03-01), Hatchett et al.
patent: 5036294 (1991-07-01), McCaslin
patent: 5095287 (1992-03-01), Irwin et al.
patent: 5271040 (1993-12-01), Clark

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