Low-power inverted ladder digital-to-analog converter

Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion

Reexamination Certificate

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C341S144000

Reexamination Certificate

active

07554475

ABSTRACT:
An inverted ladder circuit for a Digital to Analog Converter (DAC) having an input binary word representing an input value and an output current corresponding to a converted analog value. The inverted ladder circuit includes at least two fine resistor ladders, including at least an upper fine resistor ladder and a lower fine resistor ladder. The inverted ladder circuit also includes a coarse resistor ladder having a corresponding plurality of coarse ladder resistors, wherein the coarse resistor ladder slides upon the at least two fine resistor ladders. The inverted ladder circuit also includes a plurality of upper fine switches and a plurality of lower fine switches, wherein the switches operate in parallel according to the lower five bits of the input binary word. The plurality of fine ladder resistors are matched with the plurality of coarse ladder resistors to obtain current proportional to the input binary word. The output resistance and parasitic capacitance are reduced.

REFERENCES:
patent: 5252975 (1993-10-01), Yuasa et al.
patent: 5703588 (1997-12-01), Rivoir et al.
B. Razavi Principles of Data Conversion System Design, IEEE Press, 1995.
M.J.M. Pelgrom, “A 10-bit 50-MHz CMOS D/A Converter with 75-Ω Buffer,” IEEE Journal of Solid State Circuits, vol. 25, No. 6. pp. 1347-1352, Dec. 1990.
F. Maloberti et al, Power Consumption Optimization of 8-bit, 2MHz Storage Scaling Subranging CMOS 0.5μm DAC in Process IEEE Intl. Conf.on Electronics, Circuits and Systems (ICECS '96), Rodos, Greece, Oct. 1996, pp. 1162-1165.
L.E. Boylston et al, “Enhancing Performance in Interpolating Resistor String DAC's,” in Process IEEE 45th Midwest Symposium on Circuits and Systems, (MWSCAS '02), vol. 2, Aug. 2002, pp. 541-544.

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