Low-power integrated circuit with selectable battery modes

Details Low-power integrated circuit with selectable battery modes Low-power integrated circuit with selectable battery modes

1992-05-08

1994-04-26

Sikes, William L.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

3072964, 307355, 307362, 307 66, 365229, H03K 301, H02J 900

Patent

active

053069617

ABSTRACT:
An integrated circuit which can be operated EITHER in a battery-backed mode OR in a battery-operated mode. This is accomplished without any necessity for bond options, mask alteration, laser writing, or fuse blowing. The integrated circuit of the presently preferred embodiment has one pin BAT for battery input, and another pin VCCI for connection to a system power supply. Two PMOS switches are provided to connect one of these two pins to an on-chip power supply VDD under appropriate conditions. In addition, the disclosed integrated circuit has a third pin which can alternatively be used for battery input. The logic which controls the PMOS switches ensures that they will not turn on if their respective power inputs VCCI or BAT are low.

REFERENCES:
patent: 3502905 (1970-03-01), Bicking
patent: 3986051 (1976-10-01), Okada et al.
patent: 4617473 (1986-10-01), Bingham
patent: 4618857 (1986-10-01), Dubois et al.
patent: 4709202 (1987-11-01), Koenck et al.
patent: 4713555 (1987-12-01), LEe
patent: 4843224 (1989-06-01), Ohta
patent: 4908790 (1990-03-01), Little et al.
patent: 4924075 (1990-05-01), Tanaka
patent: 5010331 (1991-04-01), Dias
Search Report in PCT/US91/03376.

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