Low-power integrated circuit I/O buffer

Details Low-power integrated circuit I/O buffer Low-power integrated circuit I/O buffer

1999-12-15

2001-11-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Current driver

C327S534000, C327S537000, C327S170000, C326S087000, C326S027000

Reexamination Certificate

active

06313671

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to the field of integrated circuit products, and more specifically to a buffer circuit that consumes little power.
There is an increasing need to integrate more and more functions into integrated circuit products for lower system costs. The increase in complexity of systems implemented on a single chip requires a reduction of power consumption. Lower-power operation increases reliability and reduces system costs. In battery-operated systems, lower-power operation and lower-operating voltages are desirable to increase battery life. Chip power consumption depends on the operating voltage. The lower the operating supply voltage, the lower the power consumption in the chip. So, to reduce the power consumption in the chip, it is thus desirable to reduce the supply voltage to at least part of the chip. For example, for an integrated circuit chip made with 0.6 &mgr;m CMOS technology, the supply voltage should be reduced from 5 V nominal to 3.3 V nominal.
Where the supply voltage is 3.3V, the buffer circuit is preferably designed to withstand 5V input at an input/output (I/O) node. For example, a typical buffer circuit designed with CMOS digital integrated technology has driver PMOS transistors coupled in series between a supply-voltage VDD and an input/output node. Over-voltage can occur when a voltage at its I/O node is higher than the buffer circuit supply-voltage VDD. When a 5 V input voltage appears at the I/O node, and VDD is 3.3 V (typical value), a driver PMOS transistor can turn on if the source-to-gate voltage is greater than the PMOS threshold voltage. Also, when a 5 V input voltage appears at the I/O node, a P+/N-well diode from the I/O node to an N-well underneath the PMOS transistors turns on. As a result, the diode is forward biased and current leaks from the I/O node to the N-well.
A need therefore remains for a simple and reliable buffer circuit that consumes little power. Such a circuit should also prevent problems such as high leakage and gate-oxide damage. Specifically, the circuit should tolerate a voltage at its I/O node that is higher than the circuit supply-voltage VDD. Also, such a circuit should be cost effective and require little space.
SUMMARY OF THE INVENTION
The present invention achieves these benefits in the context of known integrated circuit technology and known techniques in the art.
The present invention provides a buffer circuit that consumes little power. Specifically, the buffer circuit can operate at lower voltages (e.g., 3.3 V) and interface with other circuits that operate at higher voltages (e.g., 5 V) at an interface node. In a preferred embodiment, the buffer circuit has a driver PMOS transistor, and a pre-driver circuit having a pull-up circuit coupled to the interface node via a PMOS switch transistor and a first PMOS pass transistor. The pre-driver biasing circuit is configured to decouple the pull-up circuit from the interface node when an input voltage at the interface node exceeds the VDD voltage by a PMOS threshold voltage. The buffer circuit has a first biasing transistor that ties an N-well of the integrated circuit to the VDD voltage source when a control node of a PMOS driver transistor is in a first logic state, and a second biasing transistor that ties the N-well to the VDD voltage source when the control node of the PMOS driver transistor is in a second logic state. In addition, the buffer circuit has a third biasing transistor that ties the N-well to the interface node when the input voltage at the interface node exceeds the VDD voltage by a PMOS threshold voltage.
In a preferred embodiment, the buffer circuit also has a second pre-driver circuit and a second driver circuit. The first and second pre-driver circuits are configured to provide control signals to a first driver circuit and a second driver circuit, respectively. The second driver circuit includes a pull-down circuit having an NMOS transistor coupled between the interface node and a VSS voltage source. The NMOS transistor has a control node configured to receive the second pre-driver control signal.
The pre-driver biasing circuit further includes a second PMOS pass transistor connected between the control node of the PMOS switch transistor and the control node of the PMOS driver transistor, a control node of the second PMOS pass transistor being coupled to the VDD voltage source; and a first pre-driver biasing transistor coupled between the second PMOS pass transistor and the VSS voltage source, a control node of the first pre-driver biasing transistor being configured to receive an enable signal; and a second pre-driver biasing transistor coupled in parallel to the first pre-driver biasing transistor, a control node of the second pre-driver biasing transistor being configured to receive a second input signal.
Yet in another embodiment, the present invention is a buffer circuit including a first feedback circuit and a second feedback circuit cross-coupled between the first and second pre-driver circuits. The first feedback circuit includes an inverter having an input coupled to a drain of the switch transistor and an output coupled to the second pre-driver circuit. The first feedback circuit also includes a PMOS transistor having a source node coupled to the VDD voltage source, a drain node coupled to the input of the inverter, and a control node coupled to the output of the inverter.
One advantage of the present invention is that it can operate under low-voltage conditions and thus consume little power. Specifically, the new design enables operation of portions of a chip at lower voltages thereby reducing the power consumption. Another advantage of the present invention is that when a high-voltage is applied to the I/O node, leakage current from I/O node to VDD is minimized. Another advantage of this design is that only one big driver PMOS is used. This saves about 4 times the area compared to that when using the alternative approach for high-voltage protection, that is, when two PMOS transistors are used in series. Another advantage of this design is that the new buffer circuit requires only a single gate-oxide thickness. This results in a significant reduction in fabrication costs and a significant increase in fabrication yield. The present invention accomplishes the above benefits and purposes in an inexpensive, uncomplicated, durable, versatile, and reliable circuit, inexpensive to manufacture, and readily suited to the widest possible utilization.
A further understanding of the nature, objects, features, and advantages of the present invention is realized upon consideration of the latter portions of the specification including the accompanying drawings and appended claims.


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