Low power I/O scheme for semiconductor memories

Details Low power I/O scheme for semiconductor memories Low power I/O scheme for semiconductor memories

1982-07-16

1986-02-11

Moffitt, James W.

Static information storage and retrieval

Powering

Conservation of power

365200, 365203, G11C 700

Patent

active

045702438

ABSTRACT:
A low power I/O scheme is described which is particularly useful in wide word semiconductor memories which include redundant memory cells as well as regular memory cells. In the present scheme, conventional load transistors for a main data bus are turned off during all write operations to conserve power. In addition, predata lines which carry data between memory cells and the main data buss include load transistors that are turned off during normal read or write operations to conserve additional power, and turned on during spare read or write operations to preserve the stability of unselected regular cells. The predata lines are also preferably held above ground potential during read or write operations to prevent conduction of deselected column select transistors.

REFERENCES:
patent: 4170741 (1979-10-01), Williams
patent: 4370737 (1983-01-01), Chan
patent: 4402066 (1983-08-01), Itoh et al.
patent: 4455627 (1984-06-01), Oritani

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