Low power, high voltage-tolerant bus holder circuit in low volta

Details Low power, high voltage-tolerant bus holder circuit in low volta Low power, high voltage-tolerant bus holder circuit in low volta

1998-05-29

1999-10-26

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327333, 326 86, H03K 190948, H03K 190175

Patent

active

059735309

ABSTRACT:
An integrated, low power bus holder circuit implemented in low voltage technology is capable of interfacing with a relatively high voltage bus. In an illustrative embodiment, the bus holder circuit includes a first inverter for inverting a logic voltage present on a data bus and a second inverter for inverting the output of the first inverter. The second inverter is comprised of a series string of first and second pFETS and first and second nFETS, with the gates of the first pFET and first nFET coupled to the output of the first inverter. The data bus is coupled to a first circuit node between the second nFET and second pFET, and the bus logic level is maintained thereat. A third pFET is coupled to the second inverter and conducts current when a high logic voltage is present on the bus. A resistance device is coupled between a drain of the third pFET and a point of low reference potential. Advantageously, the circuit arrangement of the illustrative embodiment does not draw any DC power since it avoids the use of a separate, DC power consuming biasing circuit to bias the third pFET. A fourth pFET is preferably employed to eliminate leakage current in the first inverter.

REFERENCES:
patent: 4612461 (1986-09-01), Sood
patent: 5381062 (1995-01-01), Morris
patent: 5432462 (1995-07-01), Obregon et al.
patent: 5635861 (1997-06-01), Chan et al.
patent: 5656951 (1997-08-01), Hu et al.
patent: 5723992 (1998-03-01), Yin et al.
patent: 5903180 (1999-05-01), Hsia et al.

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