Low power high voltage switch with gate bias circuit to minimize

Details Low power high voltage switch with gate bias circuit to minimize Low power high voltage switch with gate bias circuit to minimize

1995-05-19

1997-02-18

Nelms, David C.

Static information storage and retrieval

Addressing

Particular decoder or driver circuit

36518523, 365227, 365242, G11C 700, G11C 800

Patent

active

056047118

ABSTRACT:
A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.

REFERENCES:
patent: 5341329 (1994-08-01), Takebuchi
patent: 5365479 (1994-11-01), Hoang et al.
patent: 5392253 (1995-02-01), Atsumi et al.
patent: 5414669 (1995-05-01), Tedrow et al.

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