Low power/high speed static ram

Static information storage and retrieval – Powering – Conservation of power

Patent

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Details

307DIG5, 307264, G11C 1140

Patent

active

040965848

ABSTRACT:
An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. "Zero" threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

REFERENCES:
patent: 3703710 (1972-11-01), Kubo et al.
patent: 3848237 (1974-11-01), Geilhufe et al.
patent: 3906464 (1975-09-01), Lattin
patent: 3969708 (1976-07-01), Sonoda
patent: 3995172 (1976-11-01), Freeman et al.
patent: 4019068 (1977-04-01), Bormann

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