Low power, high speed receiver circuit for use in a...

Pulse or digital communications – Receivers

Reexamination Certificate

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Details

C375S362000

Reexamination Certificate

active

08045647

ABSTRACT:
A receiver circuit according to the invention includes a first phase transmission unit that is synchronized with a first clock, detects input data according to a plurality of detection levels, and transmits a first output signal, a first discharging control unit that controls a second phase transmission unit in response to the first output signal and adjusts the transmission speed of the second phase transmission unit by changing a node potential where an output of the second phase transmission is determined, and the second phase transmission unit that is synchronized with a second clock, detects the input data according to an output of the first discharging control unit, and transmits a second output signal.

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F. Bien, Y. Hur, M. Maeng, H. Kim, E. Gebara, and J. Laskar, J., “A Reconfigurable Fully-Integrated 0.18-um CMOS Feed-Forward Equalizer IC for 10-Gb/sec Backplane Links”, ISCAS 2006 pp. 2117-2120.
James E. Jaussi, Ganesh Balamurugan, David R. Johnson, Bryan Casper, Aaron Martin, Joseph Kennedy, Naresh Shanbhag, and Randy Mooney, “8-Gb/s Source-Synchronous I/O Link With Adaptive Receiver Equalization, Offset Cancellation, and Clock De-Skew”, IEEE Journal of Solid-State Circuits, Jan. 2005, pp. 80-88, vol. 40, No. 1.

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