Low power high speed MPEG video variable length decoder

Details Low power high speed MPEG video variable length decoder Low power high speed MPEG video variable length decoder

1995-12-05

1998-06-16

Young, Brian K.

Coded data generation or conversion

Digital code to digital code converters

To or from variable length codes

386109, H03M 740

Patent

active

057677999

ABSTRACT:
A variable length decoder comprises a bitstream feeder connected to a header analyzer, and a block data decoder coupled to the feeder. The bitstream feeder includes a barrel shifter to output a 32-bit bitstream to the header analyzer, block data decoder and control circuit. The header analyzer detects the start codes of the MPEG header layers and decodes the parameters of the MPEG layers contained in the encoded bitstream. Further, the header analyzer decodes the quantization factors of 8.times.8 pixel data which have been converted into 64 DCT coefficients. The block data decoder includes a macroblock decoder connected to a block decoder. The macroblock decoder outputs a header.sub.-- start signal, and activates the block decoder. The block decoder includes a code table for decoding 64 coefficients in each of the 6 block layers based on a binary pattern of a predetermined number of bits of the bitstream. The six block layers are decoded within 384 clock cycles. The control circuit monitors the functions of the bitstream feeder, the header analyzer and the block data decoder.

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