Low power, high speed analog to digital converter

Details Low power, high speed analog to digital converter Low power, high speed analog to digital converter

2002-12-18

2004-08-17

Tokar, Michael (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

C341S120000, C341S154000, C341S159000

Reexamination Certificate

active

06778124

ABSTRACT:

CROSS-REFERENCE RELATED APPLICATION
This application claims priority of Japanese Patent Application Number 2002-081042, filed Mar. 22, 2002.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an analog/digital converter, more particularly relates to a low power consumption, high conversion accuracy, high speed operation analog/digital converter.
2. Description of the Related Art
Analog/digital converters are widely used in various fields for converting analog signals to digital signals.
There are various forms of analog/digital converters. As a high speed operation type, generally a flash type is used.
A flash type analog/digital converter converts an input voltage V
i
between a top voltage V
T
and a bottom voltage V
B
to an N-bit digital signal and uses a reference voltage output circuit comprised of M number of dividing resistances R
1
to R
M
dividing the range between the top voltage V
T
and the bottom voltage V
B
into M=2
N
connected in series.
(M−1) number of voltage division points are connected to one-side terminals (for example, negative input terminals) of (M−1) number of comparators C
1
to C
M−1
. The other terminals (for example, positive input terminals) of the comparators C
1
to C
M−1
are connected in common. The input voltage V
i
is applied to the common terminal.
That is, when the input voltage V
i
is larger than V
B
+(V
T
−V
B
)/M and smaller than V
B
+2(V
T
−V
B
)/M, only the comparator C
1
arranged at the bottommost voltage V
B
side is inverted. The other comparators C
2
to C
M−1
maintain their non-inversion states.
In general, when the input voltage V
i
is larger than V
B
+(V
T
−V
B
)·(m−1)/M and smaller than V
B
+(V
T
−V
B
)·m/M, the comparators C
1
to C
m−1
at the bottom voltage V
B
side are inverted and the remaining comparators C
m
to C
M−1
maintain their non-inversion state (where, m=1, 2 . . . M).
Further, the outputs of the comparators C
1
to C
M−1
are connected to the encoder EN. The outputs of the (M−1) number of comparators are output encoded to an N-bit digital signal.
The parts of the flash-type analog/digital converter are built into an integrated circuit, but the resistance values of the M number of dividing resistances and the offsets of the (M−1) number of comparators vary and a drop in the conversion accuracy is unavoidable.
FIG. 2
is a view explaining the operating characteristic of a comparator. The abscissa indicates the differential voltage between an input voltage V
i
applied to a positive input terminal and a divided voltage applied to the negative input terminal, while the ordinate indicates the output of the comparator.
Comparators are produced designed so as to invert in output at a differential voltage of 0V, but sometimes the inversion voltage deviates from 0V due to variations at the time of fabrication of the integrated circuit. This deviation is called “offset”.
To prevent a decline in the conversion accuracy due to variation in offset, the technique is proposed of building a plurality of (for example, three) comparators into each of the comparators C
1
to C
M−1
and selecting the comparator giving the smallest offset for the conversion in the inspection or calibration process.
Even if building in a plurality of comparators, there is no guarantee that there will be a comparator with an offset of 0V. There are therefore limits to the improvement of the conversion accuracy.
Therefore, to improve the conversion accuracy, it is proposed to divide each of M number of dividing resistances R
1
to R
M
into a plurality of resistances and select the division position for supplying a reference voltage to a comparator in the inspection or calibration process to minimize the offset of that comparator (see Japanese Unexamined Patent Publication (Kokai) No. 10-65542).
FIG. 3
is a view of the configuration of an analog/digital converter of the related art to which the above technology is applied. The dividing resistances R
1
and R
M
are divided into two resistances, while the dividing resistances R
2
to R
M−1
are divided into three resistances. Further, three adjoining resistances are connected through a switch to one of the terminals of each of the comparators C
1
to C
M−1
.
On the other hand, M+1 number of reference voltages including the top voltage V
T
and bottom voltage V
B
are fed back through the switches to the input voltage terminals. Further, the output of the encoder is led to a switch control circuit SC. The switch control circuit SC controls the operation of the switches arranged between the dividing resistances and comparators and the switches for feeding back the dividing resistances to the input voltage terminals.
Further, at the calibration mode, the circuit feeds back one of the divided voltages to the input voltage terminals and selects the dividing resistances for connection to the comparators so that the corresponding comparators invert at a predetermined standard reference voltage.
Summarizing the problems to be solved by the invention, the following problems occur in an analog/digital converter of the above configuration:
(1) It is necessary to select the connection point for each comparator, so when the number of bits of the analog/digital converter is increased, time is taken for selection of the connection points.
Further, it is necessary to take into consideration the time from when switching the switches to when the outputs of the comparators stabilize, so the time required for selection of the connection points becomes further longer.
(2) If reducing the power supply voltage for reducing the power consumption of the analog/digital converter, sometimes the connection points cannot be determined.
That is, when reducing the voltage, the differential voltage between the top voltage V
T
and the bottom voltage V
B
becomes small, so the dynamic range of the input voltage also becomes small. As opposed to this, the offsets of the comparators are determined by the method of production of the integrated circuit, so the offsets become relatively large.
In the analog/digital converter of the above configuration, however, since the connection points have to be determined from limited ranges centered around standard connection points (in this embodiment, the standard connection division point and two division points above and below the same), when the offsets are large, sometimes the offsets cannot be corrected even when changing the connection points.
For example, if the differential voltage between the top voltage V
T
and the bottom voltage V
B
is V
d
and the number of bits of the digital output is N, the voltage corresponding to the least significant bit (LSB) becomes V
d
/2
N
.
When forming the comparators in an integrated circuit, the offsets are liable to become as high as 40 mV. In the analog/digital converter of the above configuration, however, the adjustable range of offset becomes 1 LSB, that is, 40 mV, so the power supply voltage must become more than 40·2
N
mV.
For example, when N=6, the power supply voltage has to be more than 40·64=2560 mV=2.56V. An analog/digital converter having a power supply voltage of 1V cannot be made.
(3) Further, since the analog/digital converter of the above configuration controls the connection and division points based on the results of encoding of the outputs of the comparators by the encoder EN, it is not possible to detect scrambling of the operating sequence of the comparators.
That is, in a flash-type analog/digital converter of the related art, the comparators have to sequentially invert along with a change in the input voltage, but sometimes the inversion sequence becomes scrambled due to the offset. For example, when the input voltage gradually rises, the comparators should invert in the sequence of C
m−1
C
m
C
m+1
, but when the offset of the comparator C
m
is large, sometimes the comparator C
m
will not invert and the

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