Low power, high SNR, high order delta sigma modulator stage...

Details Low power, high SNR, high order delta sigma modulator stage... Low power, high SNR, high order delta sigma modulator stage...

2007-03-13

2007-03-13

Barnie, Rexford (Department: 2819)

Coded data generation or conversion

Analog to or from digital conversion

Differential encoder and/or decoder

C341S144000

Reexamination Certificate

active

11246615

ABSTRACT:
In a high order delta sigma modulator stage having integrators with pipelined cross coupled input circuits, the processing delay between an upstream integrator and a downstream integrator is decreased from a full cycle of a clock used to control the high order delta sigma modulator stage to a half cycle of the clock, while the processing delay between a quantizer and a portion of a digital-to-analog converter that provides feedback to the upstream integrator is increased by a half cycle of the clock. This configuration: (1) eliminates poles from the transfer function that defines processing of a signal by the high order delta sigma modulator stage, (2) reduces the power consumed by the high order delta sigma modulator stage for a given settling time requirement, (3) facilitates reducing the size of the summing junction switches in the high order delta sigma modulator stage to decrease distortions due to charge injections, and (4) allows a reference signal voltage, which is coupled to a cross coupled feedback switched capacitor network in the integrators, to be set equal to one of two power supply voltages for the high order delta sigma modulator stage, thereby further reducing the power consumed by the delta sigma modulator.

REFERENCES:
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patent: 6111531 (2000-08-01), Farag
patent: 6535153 (2003-03-01), Zierhofer
patent: 6577259 (2003-06-01), Jelonnek
patent: 6809672 (2004-10-01), Gupta
patent: 6954162 (2005-10-01), Gupta
Chuang, S. et al., “Design and Implementation of Bandpass Delta-Sigma Modulators Using Half-Delay Integrators,”IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, IEEE Inc., vol. 45, No. 5, pp. 535-545 (May 1998).
Kasha D.B. et al., “A 16-mW, 120-dB Linear Switched-Capacitor Delta-Sigma Modulator with Dynamic Biasing,”IEEE Journal of Solid State Circuits, IEEE Solid-State Circuits Society, vol. 34, No. 7, pp. 921-926 (Jul. 1999).
Supplementary European Search Report of Appln. No. EP 03 72 3805, mailed Dec. 22, 2005, 3 pages.

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