Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-09-17
2003-07-15
Le, Thong (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060
Reexamination Certificate
active
06594195
ABSTRACT:
TECHNICAL FIELD
This invention is in the field of semiconductor integrated circuit memory devices and, more specifically, is directed to reducing power consumption in semiconductor integrated circuit random access memory devices.
BACKGROUND OF THE INVENTION
A variety of semiconductor integrated circuit memory devices are known. They offer users various combinations of speed, power and density tradeoffs. Memory arrays can be implemented as individual chip products or as components of ASICs or SOC's (embedded memory). Generally, semiconductor random access memory devices can be categorized as falling into two major categories, DRAM (dynamic random access memory) and SRAM (static random access memory). In general, one memory cell stores one bit of information. Large numbers of memory cells are organized into one or more memory arrays in a single integrated circuit, providing many millions of cells in some DRAM devices.
A conventional DRAM memory cell has one transistor and one capacitor, as illustrated in FIG.
1
. As a consequence of this simple structure, DRAM cells are typically more than 10 times smaller than an SRAM cell at the same technology generation. To write to the DRAM cell, a voltage above VCC (typically about 1V above VCC) is applied to the wordline WL while data is applied to bit line BL. The resulting voltage at the storage node is 0 or VCC. To read the cell, a voltage above VCC (typically about 1V above VCC) is applied to WL, and the voltage difference between the bit line BL and a non-selected bit line is sensed by a sense amplifier. The boosted wordline voltage is typically achieved by voltage pump circuits. Such voltage pump circuits require additional power. They also require a power-up sequence to function properly.
DRAM cells also need to be refreshed periodically. Typically the cell content is sensed against a reference voltage of VCC/2. As a cell leaks its charge, its storage node voltage level shifts from VCC or 0 towards VCC/2. The content needs to be restored periodically by refresh operation.
The amount of time allowed between refreshes depends on the leakage current of the worst cell in the entire device. The refresh frequency is nearly directly proportional to the standby power required for a DRAM device. Put another way, an increase in refresh frequency results in a corresponding increase in standby power. Standby power (and power consumption in general) is particularly important for battery-operated systems such as mobile computing and telephony devices. A conventional SRAM cell generally has four or six transistors, with three terminals, WL, BL, and BL#, as illustrated in FIG.
2
. These terminals are the wordline, bit line, and bit line complement, respectively, as is well known. To write the cell, VCC is applied to WL, and the data and its complement are applied to BL and BL#, respectively. To read the cell, VCC is applied to WL, and a voltage difference between BL and BL# is sensed by a sensing amplifier. No voltage above VCC is needed for the operation of the SRAM cell, so no voltage pumping circuits are required. And, no refresh is required; a conventional SRAM cell will retain the stored data as long as power is applied. However, the SRAM cell typically is more than 10 times larger than a DRAM cell in the same technology generation, so density is severely sacrificed.
U.S. Pat. No. 5,289,421 to Lee et al. (“Lee”) is directed to a DRAM with low noise characteristics. Essentially, Lee describes a DRAM array in which each bit or memory cell comprises not one, but two “reference memory cells” arranged between a common wordline and a pair of adjacent bitlines as illustrated in
FIG. 3
(of this application). The design proposed by Lee requires modification of the standard DRAM array which often requires modification to the manufacturing process (to connect pairs of cells to the common wordline), whereas standard array designs are available at lower cost.
A typical state-of-the-art DRAM array is shown in FIG.
4
. This is known as a folded bitline architecture. Each array is made up of M rows (wordlines) and N columns (bitlines), where M and N are both even numbers. Each wordline is connected with N/2 cells (every other cell), and each bitline is connected with M/2 cells. During an access, one of the wordlines is asserted. The charge of the N/2 cells are transferred to the N/2 bitlines. The other N/2 bitlines do not receive charge transfer and therefore act as a reference for the sensing amplifier.
What is needed is a new memory design that provides high density, like DRAM, with reduced power consumption and low cost of manufacture.
SUMMARY OF THE INVENTION
One aspect of the invention is an improved memory cell design that provides many of the advantages of SRAM with much greater density than conventional SRAM. In a presently preferred embodiment, the improved memory device employs a variation of DRAM technology to store a data bit differentially, using a pair of DRAM cells located on two different rows of the array. Thus the cells are accessed by asserting not one, but two wordlines simultaneously. No voltage boosting is necessary above VCC, so power consumption is reduced, yet read margins are improved. Since margins are improved, refresh frequency is relaxed as well, which again saves power.
More specifically, a presently preferred embodiment of the invention calls for receiving a row address; responsive to the received row address, selecting a corresponding unique pair of rows of memory cells in the DRAM array; and simultaneously accessing the selected pair of rows in the DRAM array. For a write access, for example, a data bit is written into the DRAM array by differentially storing the data bit across a pair of memory cells, each one of the pair of memory cells being within a respective one the pair of rows selected by the decoder.
A new memory product that embodies the present invention still offers 5-10 times the density of conventional SRAM as only two transistors are required per storage cell. An SRAM-pin-compatible device represents one application. Such a product is well suited to battery-powered devices such as wireless data and telecom devices. Moreover, the cost to design and deploy the new differential memory is minimized because a standard memory array (the core matrix of cells) can be used, while the necessary modifications can be made to peripheral circuits around the array, namely wordline decoder/drivers.
Additional objects and advantages of this invention will be apparent from the following detailed description of preferred embodiments thereof which proceeds with reference to the accompanying drawings.
REFERENCES:
patent: 5289421 (1994-02-01), Lee et al.
patent: 5592411 (1997-01-01), Tai
patent: 5781483 (1998-07-01), Shore
patent: 5812483 (1998-09-01), Jeon et al.
patent: 6122213 (2000-09-01), Shore
patent: 6166942 (2000-12-01), Vo et al.
patent: 6215720 (2001-04-01), Amano et al.
patent: 6285618 (2001-09-01), Shore
PCT International Search Report dated Feb. 8, 2002 for International Application No. PCT/US01/28911.
Mitsubishi Electric Data Sheet, revision-K2.0e, '99.03.10 (M5M5V408BFP, TP, RT, KV).
Fujitsu Semiconductor Data Sheet, Memory Low Power SRAM Interface FCRAM™ (MB82D01171A-90/-90L/-90LL). ©Fujitsu Limited, 2000.
Cascade Semiconductor Corporation
Le Thong
Stoel Rives LLP
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