Low power glitch-free clock switch

Details Low power glitch-free clock switch Low power glitch-free clock switch

1999-03-26

2001-09-18

Tran, Toan (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S144000, C327S407000

Reexamination Certificate

active

06292044

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the field of integrated circuit clocks, and more particularly to a low power glitch-free clock switch for selecting between a plurality of clocks in an integrated circuit.
BACKGROUND OF THE INVENTION
A single conventional integrated circuit chip can include a plurality of clocks. Only one of these clocks is selected by the circuit as the system clock at any one time. Having a plurality of clocks enables a single integrated circuit to integrate multiple systems onto one chip, wherein each system has its own clock or clocks, and the clock or clocks of each system are asynchronous to one another. The clock or clocks of one system can temporarily switch to the clock or clocks of another system so that different systems can communicate with one another synchronously. In addition, the plurality of clocks can be programmed to operate at different speeds to control power consumption.
When switching from one clock to another clock, the clock signal must either be in a low logic state (logic zero) or a high logic state (logic one) for a predetermined minimum period of time. If the clock signal is not in a low or high state for at least this minimum period of time, the circuit driven by the clock signal may be prematurely switched. Such an occurrence of a shorter than desired pulse is called a “glitch” which can impede the proper functioning of the integrated circuit.
Several conventional clock switching circuits have been developed that can select among a plurality of asynchronous clocks without producing clock glitches. However, such conventional glitch-free circuits suffer from a significant drawback. Specifically, the clock switching circuit in these circuits is active at all times, thereby unnecessarily consuming power even when switching between clocks does not occur.
SUMMARY OF THE INVENTION
A glitch-free clock switch circuit for an integrated circuit having a plurality of asynchronous clocks, wherein only one clock is selected at any one time, and wherein the clock switching circuit for switching from the selected clock to the clock to next be selected is activated only for the time it takes to complete the switching. The clock switch circuit of the present invention includes at least three sets of clock drivers, wherein a first set of clock drivers is associated with the clock output, a second set of clock drivers is associated with the currently selected clock, and a third set of clock drivers is associated with the clock to next be selected clock. An edge detector turns on these clock drivers in response to a clock select signal, and a plurality of logic gate switches the clock output from the currently selected clock to the clock to next be selected by the clock select signal. A reset circuit is provided for turning off the clock drivers once the clock output switches from the selected clock to the clock to next be selected.
The clock drivers for clocks that are not selected are not activated either during or after switching occurs from the selected clock to the clock to next be selected. Once the switching to the clock to next be selected is complete, the entire clock switching circuit is turned off until another clock switching occurs. Consequently, in situations where clock switching does not occur very frequently, significant power savings result as compared to glitch-free clock switch circuits that remain continuously.


REFERENCES:
patent: 5231636 (1993-07-01), Rasmussen
patent: 5623223 (1997-04-01), Pasqualini
patent: 5652536 (1997-07-01), Nookala et al.
patent: 5726593 (1998-03-01), Ruuskanen

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