Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Particular stable state circuit
Reexamination Certificate
1999-10-08
2001-08-21
Cunningham, Terry D. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Particular stable state circuit
C327S200000, C327S210000
Reexamination Certificate
active
06278308
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to flip-flop circuits and, more particularly, to flip-flop circuits having low power consumption, low latency, and low hold-time characteristics.
2. Description of the Related Art
Almost all modern microprocessors use a technique called pipelining to increase throughput. Pipelining involves partitioning a process with “n” steps into “n” hardware stages, each separated by memory elements called registers which hold intermediate results. These registers are typically implemented using flip-flop circuits. There is one pipeline stage for each step in the process. By allowing each of the “n” stages to operate concurrently, the pipelined process could theoretically operate at nearly “n” times the rate of the non-pipelined process.
The benefits of pipelining in a microprocessor may be diminished if the latencies associated with the inter-stage registers consume a sizable percentage of the period of the microprocessor's internal clock. The latency t
DQ
of a flip-flop circuit may be generally defined as t
SU
+t
CQ
, where t
SU
is the setup time and t
CQ
is the clock-to-valid output time. With ever-increasing clock frequencies, it is becoming increasingly important to implement inter-stage registers of microprocessors using flip-flop circuits with very low latencies.
Another important characteristic associated with the flip-flop circuits which form inter-stage registers in microprocessors is hold-time. The hold-time of a flip-flop circuit is defined as the minimum time the data input signal must be valid following a sampling clock edge. Violations in the hold-time of a flip-flop circuit may result in race conditions. Like latency, it is desirable to reduce the required hold-time characteristics of flip-flop circuits which are used to implement inter-state registers in microprocessors.
Several additional considerations may also be important in the designs of flip-flop circuits used in microprocessors. For example, it is often important to utilize flip-flop circuits which are associated with low-power consumption characteristics. Low-power consumption is particularly important for microprocessors utilized in mobile applications, such as in lap-top computers.
In addition, it is often desirable to embed logic functionality within the input section of a flip-flop circuit. However, in a typical flip-flop circuit, the addition of logic functionality at the input section creates difficulties since the symmetry in the flip-flop's differential input amplifier section may be lost. For example, a four-input NOR gating function provided on one side of the differential amplifier typically requires that a matching four-input NAND gating function be provided on the opposite side of the differential amplifier.
FIG. 1
is a schematic diagram illustrating a typical prior art flip-flop circuit. The flip-flop circuit of
FIG. 1
includes a differential stage
10
coupled to a pair of cross-coupled NAND gates
12
. The cross-coupled NAND gates
12
form an S-R latch. During operation, lines
14
and
16
of respective sides of differential stage
10
are precharged high when the clock signal CLK is low. When the clock signal CLK goes high, transistor
18
turns on, as well as one of transistors
20
or
22
, depending upon the state of input signals INL and INH (which are differential in nature). This correspondingly causes one of lines
14
or
16
to be discharged low to Vss. One of the output lines OUTL or OUTH of the flip-flop circuit is accordingly driven to a high state, and the other output is driven to a low state. These values are held through the precharge phase of a subsequent clock cycle, and may be altered in accordance with a change in the input signal during a subsequent evaluation phase. It is noted that transitions from low to high in output signal OUTL (and corresponding transitions from high to low in output signal OUTH) are caused by discharging line
14
of differential stage
10
, while transitions from low to high in output signal OUTH (and corresponding transitions from high to low in output signal OUTL) are caused by discharging line
16
of differential stage
10
.
Implementations of the flip-flop circuit of
FIG. 1
may be associated with relatively high latency and hold-time characteristics, as well as relatively high power consumption characteristics. This is due in part to the fact that both sides of the differential stage are used to control the state of the cross-coupled NAND gates
12
, thus requiring that the transistors forming each side of differential stage
10
be of sufficient size to drive cross-coupled NAND gates
12
.
It would be desirable to provide a flip-flop circuit which is associated with low power consumption, low latency, and low hold time characteristics. Additionally, it would be desirable to provide a flip-flop circuit which readily accommodates complex input logic.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a flip-flop circuit in accordance the present invention. In one embodiment, a flip-flop circuit includes a differential stage coupled to a transparent latch. Respective sides of the differential stage, referred to as the “output side” and the “reference side,” are precharged high during a precharge phase. During an evaluation phase, the state of a data input signal is sensed. Depending upon the state of the data input signal, either the output side or the reference side is discharged. Also, during the evaluation phase, the transparent latch is enabled, and thereby samples and stores an output signal from the output side of the differential stage. Upon initiation of the next precharge phase, the transparent latch is quickly disabled (i.e., is placed in an opaque state), and retains its present state.
Since only a single side of the differential stage is used to drive the transparent latch, the differential stage may advantageously be implemented in an asymmetric fashion. More particularly, transistors forming the reference side of the differential stage may be fabricated using smaller channel widths than corresponding transistors forming the output side of the differential stage. This advantageously allows high speed implementation s of the flip-flop circuit while reducing latency, hold-time, and power consumption.
The flip-flop circuit may include a clock conditioning circuit which receives an input clock and generates a corresponding differential clock signal for controlling occurrences of the precharge and evaluation phases of the differential stage. The clock conditioning circuit further generates a latch clock signal which selectively enables the transparent latch. In one embodiment, the clock conditioning circuit is configured to generate the latch clock signal such that it quickly disables the transparent latch at the start of a precharge phase of the differential stage. A transition in the latch clock signal which causes the transparent latch to be enabled is, however, delayed somewhat with respect to the differential stage clock signal such that the latch is held in an opaque state until the differential stage resolves according to the data input signal. This may advantageously prevent unwanted “glitches” in the output of the flip-flop circuit.
In yet an additional embodiment, complex logic may be added to the differential stage of the flip-flop circuit. Due to the asymmetric nature of the transistors forming the differential stage, the complex logic generates a gating signal to control only the output side of the differential stage. The reference side of the differential stage is gated by a clock signal (e.g., the differential stage clock signal). This thereby eliminates the need for matching logic to generate a corresponding gating signal to control the reference side of the differential stage.
REFERENCES:
patent: 5712826 (1998-01-01), Wong et al.
patent: 5764089 (1998-06-01), Partovi et al.
patent: 5917355 (1999-06-01), Klass
patent: 5933038 (1999-08-01), Klass
Montanaro, et al., “A 160-MHz, 32-b, 0.5-W CMOS
Golden Michael
Partovi Hamid
Yong John
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Cunningham Terry D.
Kivlin B. Noäl
Tra Anh-Quan
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