Low power flip-flop circuit and method thereof

Details Low power flip-flop circuit and method thereof Low power flip-flop circuit and method thereof

1994-11-25

1996-03-12

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327225, 327230, H03K 3037

Patent

active

054989884

ABSTRACT:
A low power flip-flop circuit is disclosed including a clocked flip-flop (10) and switching circuit (40, 60) with control inputs coupled to the data input and data output of the flip-flop to determine whether or not the data input to the flip-flop is changing. Any clock pulse during periods when the data input is not changing consumes power without providing a useful function. The switching circuit passes clock pulses to a clock input of the flip-flop only when new data is present to be latched into the flip-flop, i.e. data input state and data output state disagree. The switching circuit blocks clock pulses to the flip-flop when the data to the flip-flop is not changing and thereby saves power consumption.

REFERENCES:
patent: 4348597 (1982-09-01), Weber
patent: 4631420 (1986-12-01), Hollis et al.
patent: 4864243 (1989-09-01), Reese
patent: 5144168 (1992-09-01), Tran
patent: 5233617 (1993-08-01), Simmons et al.
patent: 5357144 (1994-10-01), Tanaka
patent: 5410550 (1995-04-01), Simmons et al.

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