Low power flip flop

Details Low power flip flop Low power flip flop

2003-05-30

2004-10-12

Lam, Tuan T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S203000, C327S218000

Reexamination Certificate

active

06803799

ABSTRACT:

FIELD OF THE INVENTION
The present disclosure relates to D type flip flops and more particularly to a low power, high efficiency flip flop capable of operating at high frequencies.
BACKGROUND OF THE INVENTION
Battery powered operation and low voltage digital circuits have motivated the design of low voltage and extremely efficient analog circuits. Analog integrated circuits are generally implemented using transistor based components which include logic devices. The capabilities of these transistor based circuits and logic devices have a substantial bearing on integrated circuit performance.
A conventional D-type flip flop is one example of a logic circuit contained on a fabricated integrated circuit Flip flops of this type would be used as registers and in applications such as frequency dividers, counters, shift registers (excluding the first, externally connected, element), state machines and so on.
A prior art D type flip flop
10
is shown in FIG.
1
. As is conventional, the flip flop
10
has a “D” input signal line, an output line “Q”, and inverted output line “QB”, and a clock input terminal “CLOCK”. The input into the D line is stored and output as a signal Q until the state of the flip flop is changed by applying a different signal on the D input and applying the clock signal.
The operation of a conventional prior art D type flip flop is described in reference to
FIG. 2
The circuit in
FIG. 2
is one example of how a D type flip flop may be realized using pass transistor based circuitry. As shown in
FIG. 1
, the flip flop
11
in
FIG. 2
also has a “D” input signal line, an output line “Q”, and inverted output line “QB”, and a plurality of clock input terminals “C” and “CB”. The clock and inverted clock signals C and CB are used to control a plurality of transmission gates within the flip flop
11
.
FIG. 2
contains tour CMOS inverters
12
,
14
,
16
and
18
, four transmission gates TX
1
, TX
2
, TX
3
, and TX
4
, along with two inverters
13
and
15
used to produce the clock and inverted clock signals C and CB. The circuit is constructed so that inverters
12
and
14
along with transmission gate TX
2
form a memory element. Similarly
16
,
18
and TX
4
form a second memory element. Both of these memory elements are capable of storing either a one or zero state.
Referring to
FIG. 2
, when a CLOCK signal is low, the transmission gate TX
1
is on, while transmission gate TX
2
is off. The signal present at the input D passes through TX
1
,
12
and
14
, and is present at node
1
. When TX
3
is off, node
1
is isolated from node
2
and the output node Q and QB. Keeping nodes
1
and
2
electrically separated enables the memory elements to function independently. When TX
4
is on,
16
and
18
are in closed feedback loop so
16
,
18
and TX
4
are configured as a memory element, where Q and QB are the outputs of this memory element. When the CLOCK signal goes high, input D is isolated from the rest of the circuit. The last state of input D prior to the CLOCK going high is now latched by inverters
12
,
14
and transmission gate TX
2
(which is now ON). Transmission gate TX
3
is now also on (TX
4
is off), hence output Q is forced to the same logic level as the input pin D before the clock went high. This output state will be retained until a new level for D is latched by the CLOCK signal going through another low to high transition.
Referring to
FIG. 3
, circuit
20
illustrates a standard prior art CMOS inverter that may be used as the inverters in FIG.
2
. This simple inverter contains an NMOS and PMOS transistor
22
and
21
respectively. This type of inverter produces an OUT signal that is an inversion or opposite of the IN signal. A drawback of this simple inverter is the cross-over currents (between the transistors
21
and
22
) that are produced when the input to the circuit
20
changes. Ideally only one of the two transistors
21
or
22
should be on at any given time, however during an input transition, momentarily both transistors are on, allowing a high current to flow from the supply to ground. Cross-over current is wasted power, it contributes no useful function and should therefore be minimized or eliminated in applications where power consumption is of concern.
Referring to
FIG. 4
, another prior art inverter
30
is shown which has current limiting techniques added to improve the power consumption of the device. This circuit includes PMOS transistors MP
1
, MP
2
, MP
3
and MP
4
. The inverter
30
also contains NMOS transistors MN
1
, MN
2
, MN
3
and MN
4
. The function of this circuit is the same as that in
FIG. 3
, the signal output (at the OUT terminal) is an inversion of the signal coming into the circuit (applied to the IN terminal). When the incoming signal changes states, both the NMOS and PMOS transistors MN
2
and MP
2
may both be temporarily on thereby creating undesirable cross-over currents. In this circuit arrangement of
FIG. 4
, bias currents are set so that the cross currents between the NMOS and PMOS devices are limited As mentioned before, limiting the current will improve the power efficiency of the device
In this circuit MP
2
and MP
2
form the inverter part of the circuit (as in FIG.
3
). Transistors MP
1
and MN
1
are connected to function as current limiting devices Transistors MP
3
and MP
4
are used to set the bias currents for MP
2
, while MN
3
and MN
4
are used to set the bias current for MN
2
. The cross over currents between MP
2
and MN
2
are now limited to Ibias. The voltage between the gate and source electrodes of these devices is set using a current mirror such that the maximum drain-source current (Ids) is equal to the bias current Ibias. This inverter has crossover currents limited to Ibias, so is relatively power efficient. However, the speed of operation is determined by the current available to charge and discharge a capacitive load, which in
FIG. 2B
is now also limited to Ibias.
Besides cross-over currents, a second source of inefficiency exists which is common to all prior art D-type flip flops. This inefficiency arises because the possibility exists that the outputs of the 2 memory element stages will drive each other, giving rise to significant supply currents during clock transitions.
Therefore there exists a need for a low current, power efficient, D type flip flop that is capable of operating at high switching speeds.
SUMMARY OF THE INVENTION
A low power, high speed D-type flip flop is disclosed. The D type flip flop uses four inverters and four transmission gates to store and output the data states of the flip flop. The flip flop contains two memory elements wherein each memory element is formed from a transmission gate connected in parallel with two inverters. Each of the four inverters is referred to as a bypass current limiting inverter. Each of the four inverters contains biasing circuitry to limit current flow and thereby save power. Additionally, each inverter has switching circuitry that enables the current limiting features to be selectively bypassed thereby allowing for large currents and fast response times.
Each inverter stage of the flip flop is connected such that the preceding (in time) memory element configures the inverters in the following element to enable fast operations, yet limit crossover currents in each inverter The limiting current is determined to be a compromise between the maximum crossover current and the strength of the ‘weak’ side of the inverter (i.e., its resilience to having its output driven).
Finally, to avoid the outputs of the memory elements driving each other, the transmission gates are driven by non-overlapping clocks. Non-overlapping clocks eliminate the possibility of the outputs being momentarily connected together so that the states of the memory elements may be correctly latched as the output of the flip flop device.
Specifically, the flip flop of the present invention comprises a first access transmission gate in series with a first memory element comprising a second transmission gate connected in parallel with first and s

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