Low power flip-flop

Details Low power flip-flop Low power flip-flop

1995-05-26

1998-08-04

Ton, My-Trang Nu

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

327203, 327208, H03K 3289, H03K 3356

Patent

active

057899568

ABSTRACT:
A flip-flop circuit which includes a master section (1) having a pair of back to back connected inverters (5, 7) to form a latch circuit with their ground terminals connected together. The clock signal is coupled to the ground terminal of the inverters (5,7) to provide a negative gate to source voltage rather than an essentially zero gate to source voltage as used in prior art inverters to insure full turn off of the inverter transistors (40, 45) during their off periods and conserving power thereby. When the first phase of the clock signal goes high, the signal on the data line is fed to one side of the latch and the other side of the latch is coupled to ground or reference voltage. When the first phase of the clock then goes low, the signal from the data line is latched into the latch of the master section (1) and the other side of that latch is decoupled from ground. Also, when the first phase of the clock signal goes low and the second phase of the clock signal concurrently goes high, the signal latched in the latch of the master section (1) is fed to the slave section (3). The slave section (3) is identical to the master section (1) except that the clock signals received are of opposite phase or state to the clock signals received by the master section (1) and the input to the slave section (3) is the signal latched into the latch of the master section (1). The signal stored in the latch of the slave section (3) is the output of the flip-flop.

REFERENCES:
patent: 4656368 (1987-04-01), McCombs et al.
patent: 4794276 (1988-12-01), Sasada et al.
patent: 4806786 (1989-02-01), Valentine
patent: 5212411 (1993-05-01), Asazawa
patent: 5264738 (1993-11-01), Veendrick et al.
patent: 5281865 (1994-01-01), Yamashita et al.
patent: 5508648 (1996-04-01), Banik
patent: 5552738 (1996-09-01), Ko
Kojima et al., "Half-Swing Clocking Scheme for 75% Power Saving in Clocking Circuitry," 1994 Symposium on VLSI Circuits Digest of Technical Papers, IEEE Cat. No. 94CH3434-8, Jun. 1994, pp. 23-24.

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