Low power dual processor architecture for multi mode devices

Details Low power dual processor architecture for multi mode devices Low power dual processor architecture for multi mode devices

2002-08-27

2008-11-11

Sobutka, Philip J (Department: 2618)

Telecommunications

Transmitter and receiver at same station

Radiotelephone equipment detail

C455S556100, C455S574000, C455S343100

Reexamination Certificate

active

07450963

ABSTRACT:
A mobile computing device with multiple modes, for example, wireless communication and personal computing, has an application processor and a communication processor. In the computing mode, the application processor is the master processor. In the communication mode, the application processor is deenergized to conserve battery power, with the communication processor functioning as the master processor by accessing the device's peripheral bus using the memory interface of the communication processor.

REFERENCES:
patent: 5487181 (1996-01-01), Dailey et al.
patent: 5870680 (1999-02-01), Guerlin et al.
patent: 5925092 (1999-07-01), Swan et al.
patent: 6731958 (2004-05-01), Shirai
patent: 2002/0032039 (2002-03-01), Kimata
patent: 2002/0173344 (2002-11-01), Cupps et al.
patent: 2003/0008690 (2003-01-01), Guterman
patent: 2003/0017854 (2003-01-01), Avitan
patent: 2003/0163798 (2003-08-01), Hwang et al.

Affiliated with

Also associated with

Rating

Low power dual processor architecture for multi mode devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power dual processor architecture for multi mode devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power dual processor architecture for multi mode devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4030964