Low power dissipation combined enhancement depletion switching d

Details Low power dissipation combined enhancement depletion switching d Low power dissipation combined enhancement depletion switching d

1976-02-24

1977-08-16

Heyman, John S.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307205, 307214, 330 35, H03K 1908, H03K 1940, H03K 1704, H03K 1710

Patent

active

040428397

ABSTRACT:
In a push-pull output circuit comprising inverters, each using a depletion-type load field-effect transistor (FET) and an enhancement-type driving FET, an intermediate inverter including a depletion-type load FET and an enhancement-type driving FET is added between the input side and output side inverters. The load impedance of the output side inverter is set at a value much smaller than those of the other inverters. The utilization of a power supply voltage is enhanced because of the use of depletion-type FET's and the total current in the circuit is low due to the use of the intermediate inverter.

REFERENCES:
patent: 3700981 (1972-10-01), Masuhara et al.
patent: 3775693 (1973-11-01), Proebsting
patent: 3778784 (1973-12-01), Karp et al.
Aoki et al., "Field-Effect Transistor Driver Circuit," IBM Tech. Discl. Bull., vol. 17, No. 7, pp. 2066-2067, 1974 (Dec.).

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