Low power dissipation autozeroed comparator circuit

Details Low power dissipation autozeroed comparator circuit Low power dissipation autozeroed comparator circuit

1992-11-30

1995-02-21

Callahan, Timothy P.

Miscellaneous active electrical nonlinear devices, circuits, and

Specific signal discriminating without subsequent control

By amplitude

327 65, H03K 524

Patent

active

053919378

DESCRIPTION:

BRIEF SUMMARY
DESCRIPTION

The present invention relates to a low power dissipation autozeroed comparator circuit suitable for CMOS integration.
As known, a comparator circuit receives at its input a constant reference signal and a signal generally variable in time, and produces a square-wave signal representing the times during which the level of the variable signal is higher (or lower) than the threshold represented by the reference signal.
The operation of an autozeroed comparator occurs in two times or phases, an autozero phase .PHI.1 where the circuit initial conditions are reset, and phase .PHI.2 where the input signal Vin is compared to the reference signal Vref.
Comparators are used in a variety of digital processing systems requiring a conversion interface.
CMOS comparators with autozero-phase designed through switched capacitors (SC) technique, are already well known.
FIG. 1 shows a known circuit of this type, consisting of two cascaded autozeroed inverters, followed by a so-called latch L. A comparator of this type is also disclosed in U.S. Pat. No. 3,676,702.
The basic structure, shown inside the dotted section of FIG. 1, includes two transistors MA1 and MA2, n channel and p channel respectively, connected in series between two voltages V.sub.DD and V.sub.SS, whose gates are shorted. To the gates common node one of plates of comparator input capacitor C1, is connected. Two switches S1 and S2 are foreseen to connect alternatively and subsequently the other plate of capacitance C1 to an input voltage Vin and to a reference voltage Vref, respectively.
The gates common node is connected to capacitance C2 of the subsequent stage through a switch S3, this stage being alike to the previous one and formed by components C2, MA3, MA4 and S4.
In autozero operation (during which the switch S3 is closed) the two transistors MA1 and MA2 are biased in the saturation range with high voltage between gate and source V.sub.GS equal to approx (V.sub.DD -V.sub.SS)/2.
This condition causes a high bias current Ip to flow through the transistors MA1 and MA2 and, consequently a considerable power dissipation.
One of the objects of the present invention is therefore to eliminate or at least to limit this disadvantage of the present known autozeroed comparators, and in particular to realize a low power dissipation circuit, suitable for integration in CMOS technology.
Another object of the invention is to propose a comparator having improved performances, in particular able to obtain an advantageous compromise between operation speed and power dissipation, together with improved sensitivity performances.
These objects are achieved with the comparator of this invention consisting of an autozeroed comparator circuit, including a first amplifier stage whose input can be selectively connected to an input voltage and to a reference voltage; a second amplifier stage connected to the output of the first amplifier stage; and a final stage, connected to the output of said second amplifier stage at which output a rectangular signal is present, representing the times during which the input signal is higher than the reference signal, characterized by the fact that the two amplifier stages are identical, and include a first inverter and a second inverter respectively, driven by a first follower circuit and a second follower circuit respectively; having one plate that is selectively and not simultaneously connectable, via two controlled input switches, to said reference voltage and to said input voltage, respectively, and the other plate thereof connected to the gate of a first transistor of the first follower circuit, a first controlled switch being provided one plate connected to the output of said first stage, and the other plate thereof connected to a second transistor of the second follower circuit, a second controlled switch being provided between said other plate and the output of said second stage.
According to the above it can be noted that the inverter in U.S. Pat. No. 3,676,702 is formed by a pair of MOSes, with opposite conductive channe

REFERENCES:
patent: 3676702 (1972-07-01), McGrogan, Jr.
patent: 4028558 (1977-06-01), Heller et al.
patent: 4211942 (1980-07-01), Aoki et al.
patent: 4695748 (1987-09-01), Kumamoto

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