Low-power decode circuitry and method for a processor having...

Details Low-power decode circuitry and method for a processor having... Low-power decode circuitry and method for a processor having...

2007-03-20

2007-03-20

Sparks, Donald (Department: 2181)

Electrical computers and digital processing systems: processing

Instruction decoding

Decoding instruction to accommodate plural instruction...

C712S032000, C712S043000

Reexamination Certificate

active

10406742

ABSTRACT:
A processor includes first decoder logic capable of decoding a plurality of encoded instructions comprising a first instruction set, the first decoder logic having an input to receive an encoded instruction output from the fetch logic. The processor also includes second decoder logic capable of decoding a plurality of encoded instructions comprising a second instruction set, the second decoding logic having an input to receive an encoded instruction output from the fetch logic. Finally, the processor includes decoder control logic configured to selectively control active operation of the first decoder logic and the second decoder logic. In operation, the decoder control logic operates such that when the first decoder logic is decoding an instruction then the second decoder logic is operated in a lower-power, inactive mode. Likewise, when the second decoder logic is decoding an instruction then the first decoder logic is operated in a lower-power, inactive mode.

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