Low power data translation circuit and method of operation

Details Low power data translation circuit and method of operation Low power data translation circuit and method of operation

1995-07-24

1997-04-01

Nelms, David C.

Static information storage and retrieval

Associative memories

Ferroelectric cell

36518901, 36523001, 365227, G11C 1500

Patent

active

056173482

ABSTRACT:
A low power circuit (10) for translating logical addresses or input data to corresponding physical addresses or output data respectively. The circuit (10) includes an input latch (12), content addressable memory (CAM) (14), random access memory (RAM) (16), output latch (18), and comparator (20). The input latch (12) receives the logical address (22) and stores the logical address for at least one comparison cycle. The CAM (14) receives the logical address (22) and produces a corresponding match signal. The RAM (16) receives the corresponding match signal and produces the corresponding physical address (28). The output latch (18) receives the corresponding physical address (28) and stores the value for at least one clock cycle. The comparator (20) enables the CAM (14) and/or the RAM (16) operation only when the previous logical address does not match the current logical address (22). The corresponding physical address (28) remains in the output latch (18) until such time as a new logical address (22) or input data is provided to the low power circuit (10).

REFERENCES:
patent: 5239642 (1993-08-01), Gutierrez et al.
patent: 5280449 (1994-01-01), Oldham
patent: 5329629 (1994-07-01), Horst et al.
patent: 5564052 (1996-10-01), Nguyen et al.

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