Low-power data serializer

Details Low-power data serializer Low-power data serializer

2001-02-14

2002-07-09

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Digital code to digital code converters

Parallel to serial

C326S096000, C326S093000, C326S044000

Reexamination Certificate

active

06417790

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to high-speed serial data transceivers and, in particular, high-speed data serializers.
Serial data communication circuits use data serializers for converting a plurality of parallel data inputs to a single serial data stream. A typical data serializer includes a time-division data multiplexer, which sequentially multiplexes the parallel data outputs to a single output. The sequential selection of data inputs is controlled by a clock circuit which has two or more phases. A typical multi-phase clock circuit generates n select clock signals. The n select clock signals are equally distributed in phase over 360 degrees. The select clock signals are used to select individual data inputs in a particular order.
SUMMARY OF THE INVENTION
A data serializer according to one embodiment of the present invention includes a differential output stage. The differential output stage has n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of n parallel data inputs. Each pair of first and second control inputs is driven by first and second logic AND circuits having only p-channel output drive transistors.
One aspect of the present invention is directed to a data serializer, which includes n data inputs, n clock inputs, a differential output stage and an input stage. Each clock input is out of phase with the other clock inputs and corresponds to one of the n data inputs. The differential output stage has first and second differential data outputs and n pairs of first and second control inputs, wherein each pair of control inputs corresponds to one of the n data inputs. The input stage includes, for each of the n data inputs, a first logic AND circuit and a second logic AND circuit. The first logic AND circuit has first, second and third inputs which are coupled to the data input, the corresponding clock input and an inverse of the clock input that next trails the corresponding clock input in phase, respectively, and an output which is coupled to the first control input of the corresponding pair of control inputs through p-channel drive transistors. The second logic AND gate circuit has first, second and third inputs which are coupled to an inverse of the data input, the corresponding clock input and the inverse of the clock input that next trails the corresponding clock input in phase, respectively, and an output which is coupled to the second control input of the corresponding pair of control inputs through p-channel drive transistors.
Another aspect of the present invention is directed to a method of serializing a parallel data input having n data inputs. The method includes providing n differential transistor pairs in parallel with one another, between first and second differential data outputs and a tail current source. Each transistor pair has a respective pair of first and second control inputs. The method further includes receiving the n data inputs and n clock signals, wherein each clock signal is out of phase with the other clock signals and corresponds to one of the n data inputs. For each of the n data inputs received, the respective pair of first and second control inputs is driven between first and second voltage levels using p-channel driving transistors based on logic states of the corresponding data input, the corresponding clock signal and the clock signal that next trails the corresponding clock signal in phase.


REFERENCES:
patent: 5955897 (1999-09-01), Narayana et al.
patent: 6087855 (2000-07-01), Frederick, Jr. et al.
patent: 6268746 (2001-07-01), Potter et al.
patent: 6271682 (2001-08-01), Lindsay

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