Low power CSD linear phase FIR filter architecture using...

Details Low power CSD linear phase FIR filter architecture using... Low power CSD linear phase FIR filter architecture using...

2006-03-21

2006-03-21

Malzahn, D. H. (Department: 2193)

Electrical computers: arithmetic processing and calculating

Electrical digital calculating computer

Particular function performed

Reexamination Certificate

active

07016926

ABSTRACT:
A method for implementing a low power and high-speed digital filter having reduced number of adders is disclosed. The method comprises the steps of determining vertical common CSD (Canonical Signed Digit) code words between corresponding CSD code words of adjacent filter coefficients, wherein a vertical common CSD code word in a highest level bit is set as a vertical common subexpression, expressing the vertical common CSD code words out of the CSD code words of each filter coefficient with the vertical common subexpression by shifting and delaying the vertical common subexpression, and synthesizing the expressed vertical common CSD code words of the filter coefficients.

REFERENCES:
patent: 5058047 (1991-10-01), Chung
patent: 5831880 (1998-11-01), Lee
patent: 6163788 (2000-12-01), Chen et al.
patent: 6678709 (2004-01-01), Gandhi et al.
patent: 6757326 (2004-06-01), Prieto et al.
patent: 2002/0152251 (2002-10-01), Jang

Affiliated with

Also associated with

Rating

Low power CSD linear phase FIR filter architecture using... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low power CSD linear phase FIR filter architecture using..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low power CSD linear phase FIR filter architecture using... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3575204