Electrical pulse counters – pulse dividers – or shift registers: c – Applications – Including memory
Reexamination Certificate
1999-05-13
2001-07-31
Wambach, Margaret R. (Department: 2816)
Electrical pulse counters, pulse dividers, or shift registers: c
Applications
Including memory
C377S034000, C377S116000
Reexamination Certificate
active
06269138
ABSTRACT:
The present invention generally relates to counters and counter blocks and more particularly to low power counters and counter blocks.
BACKGROUND
Counters are used in many different electronic apparatuses such as computers, calculators, personal organisers, mobile phones etc.
A counter is a sequential machine designed to cycle through a predetermined sequence of states in response to pulses on an input line. The states usually represent consecutive numbers. There are many different counters available depending on the number code used, the modulus, and the timing mode.
Counters can be either synchronous or asynchronous (or ripple clock counters).
A conventional 4-bit or modulo-16 binary counter is composed of four JK flip-flops. The counter counts pulses on the count enable line or clock input. The output is a 4-bit binary number. A synchronous counter is characterized in that the count enable line of every flip-flop is connected to the same clock source.
In an asynchronous counter the output of some flip-flops is connected to the count enable input of its right neighbour or the more significant bit so that it may alter the state of that neighbour flip-flop. Thus, carry signals ripple through the counter from left to right. Therefore, an asynchronous counter is also called a ripple counter.
A problem with the above mentioned prior art counter designs is that when they are used in applications or apparatuses, such as mobile phones, where power consumption is critical, the power consumption in the flip-flops in the counters is a considerable portion of the total power consumption in the current apparatus.
U.S. Pat. No. 5,585,745 discloses methods and apparatus for reducing the power consumption of personal computers. A power controller reduces power by deactivating functional blocks that are not needed as indicated by clock control signals. Control signals are received from a number of functional blocks, a particular functional block is deactivated upon a request from that functional block or from another functional block, and the particular functional block is activated upon request from another funtional block. Each functional block consumes less power when deactivated than when activated. Preferably, the functional blocks are activated by applying a full-speed clock to the functional block, and are deactivated by not applying the clock to the block. This is accomplished with a “modulated clock” which is derived from a regular output clock as modulated by signals supplied by the clock control lines.
However, U.S. Pat. No. 5,585,745 describes merely functional blocks in general and not a particular kind of block level or block size.
SUMMARY
An object of the present invention is to provide low power counters and counter blocks in order to reduce the power consumption problem.
This is accomplished by the low power counter according to the invention having low power counter blocks comprising flip-flops consuming a minimum of power when they are disabled and which are activated only when the value of the respective data output connection has to be changed.
Another object of the invention is to provide a low power n-bit binary coded counter (n−1 . . . 0) using low power binary counter blocks according to the invention, wherein bit i is changed and the flip-flop in the current block corresponding to the bit i is activated only if bit i−1 to 0 are all equal to “1”.
Still another object of the invention is to provide a low power n-bit gray coded counter using low power gray coded counter blocks according to the invention. Two consecutive states representing two n-bit gray coded words (n−1 . . . 0) are called s0 and s1. In order to determine a word S2 in the state following the state presenting the word S1 the counter performs the following operations. Bit i (i<>n−1) is changed from s1 to s2 and the flip-flop in the block corresponding to the bit i is activated only if bit i in s1 and s0 are equal, bit i−1 in s1 is equal to “1”, and bit i−2 to 0 in s1 are equal to “0”. Bit n−1 is changed from s1 to s2 and the flip-flop in the block corresponding to the bit n is activated if bit n−1 in s1 and s0 are equal, and bit n−3 to 0 in s1 are equal to “0”.
An advantage of the low power counters according to the invention is the reduction of power consumption.
REFERENCES:
patent: 3783306 (1974-01-01), Hoffman
patent: 4780894 (1988-10-01), Watkins et al.
patent: 5164968 (1992-11-01), Otto
patent: 96/25701 (1996-02-01), None
IBM Technical Disclosure Bulletin, vol. 7, No. 7, Dec. 1964, A. Cutaia, “Gray Code Generator”, pp. 587-588.
Burns Doane Swecker & Mathis L.L.P.
Telefonaktiebolaget LM Ericsson (publ)
Wambach Margaret R.
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