Low power control circuit and method for a memory device

Details Low power control circuit and method for a memory device Low power control circuit and method for a memory device

2006-04-04

2006-04-04

Elms, Richard (Department: 2824)

Static information storage and retrieval

Powering

C365S227000, C365S189050

Reexamination Certificate

active

07023755

ABSTRACT:
A memory device with a low power control circuit that reduces power while ensuring that the device remains in a low power mode until a high power mode has been requested. The low power control circuit initially monitors a control signal using a CMOS buffer or inverter while a reference voltage is grounded or floated. Upon CMOS detection of a signal indicating that a high power mode is required, the low power control circuit monitors the signal using a differential amplifier and the specified reference voltage (i.e., ungrounded and un-floated reference voltage) to determine if the low power mode should be exited. In doing so, the low power control circuit prevents noise from inadvertently causing the device to exit the low power mode while at the same time reduces the power in the device.

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patent: 6058063 (2000-05-01), Jang
patent: 6549479 (2003-04-01), Blodgett
patent: 6603698 (2003-08-01), Janzen
patent: 6816994 (2004-11-01), Schoenfeld et al.

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