Low power content addressable memory array (CAM) and method...

Details Low power content addressable memory array (CAM) and method... Low power content addressable memory array (CAM) and method...

2005-08-12

2009-02-03

Le, Thong Q (Department: 2827)

Static information storage and retrieval

Associative memories

C365S049160, C365S185170, C365S049170, C365S203000, C365S189110

Reexamination Certificate

active

07486531

ABSTRACT:
A content addressable memory (CAM) system that includes a row of NAND-type CAM cells divided into a plurality of segments. Each segment includes a plurality of series-connected switching transistors, wherein each of the switching transistors is part of a corresponding NAND-type CAM cell. The series-connected switching transistors of each segment are coupled to the series-connected switching transistors in an adjacent segment by a repeater circuit, thereby forming a chain of series-connected switching transistors and repeater circuits. A match line driver circuit is coupled to one end of the chain, and a match line is connected to the other end of the chain. If a match condition exists for the entire row, then a signal driven by the match line driver is propagated to the match line, through the chain of series-connected switching transistors and repeater circuits.

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