Low power consumption word line driver

Details Low power consumption word line driver Low power consumption word line driver

1991-08-06

1993-11-16

LaRoche, Eugene R.

Static information storage and retrieval

Powering

Conservation of power

307443, 307448, 307450, G11C 700, H03K 1908

Patent

active

052630013

ABSTRACT:
Disclosed is a low power consumption word line driver that satisfactorily operates even with the threshold voltage variations. A load FET comprises a depletion FET (J5) and enhancement FET (J6). The drain, gate and source of the depletion FET are connected in parallel to those of the enhancement FET. An enhancement FET (J7) is provided to charge a word line. The drains of the depletion FET and enhancement FET J5 and J6 are connected to ground voltage, the gates to the series connecting point of the preceding circuit part, and the sources to the drain of the drive FET J7 for output. The source of the drive FET J7 is connected to voltage source.

REFERENCES:
patent: 4042839 (1977-08-01), Araki
patent: 4503341 (1985-03-01), Shah
patent: 4714840 (1987-12-01), Proebsting
patent: 4755695 (1988-07-01), Suzuki

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