Low power consumption type digital logic circuit

Details Low power consumption type digital logic circuit Low power consumption type digital logic circuit

2000-05-30

2002-02-26

Le, Dinh T. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Particular stable state circuit

C327S198000

Reexamination Certificate

active

06351170

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a logic circuit and more particularly to a logic circuit provided with a gate in a clock supplying line and a semiconductor logic integrated circuit.
2. Description of the Related Art
In a digital logic circuit (hereinafter also referred to as a logic circuit) in which a clock frequency is approximately proportional to power consumption, one method to lower the power consumption of the logic circuit is to use, a gated clock type logic circuit in which a gate circuit is inserted into a clock supplying line and a supply of a clock is suspended while the logic circuit is not operating. By using this method, if, for example, an average clock frequency can be reduced by a factor of ten by the suspension of the supply of clock, the power consumption of the digital logic circuit is lowered approximately by the factor of ten as well, thus achieving greatly lowered power consumption.
However, a conventional logic circuit (also referred to as a gated clock type logic circuit) has the following problems.
In the digital logic circuit, an occurrence of spike noise in the clock supplying line causes a malfunction in the logic circuit. When the gate circuit is inserted into the clock supplying line, if a full adjustment of operational timing at a time of designing had not been made, there would be a possibility of the occurrence of spike noise in the clock supplying line. That is, the gated clock method presents a problem in that there is difficulty in designing of operational signal timing and much time is required for the designing and adjustment of the timing.
FIG. 14
is a schematic block diagram showing one example of configurations of a conventional gated clock type logic circuit. As shown in
FIG. 14
, a data input DATA (
1
) is inputted to a data input terminal D of a D-type flip flop
1
and a clock is inputted to a clock input terminal C of flip-flop
1
. A data output DATA (
0
) is outputted from an output terminal Q. The clock input terminal C is connected to an output from a gate circuit
2
in which a clock enabling signal and a clock signal are inputted to its input terminals. The clock enabling signal is supplied from an output Q of a D-type flip flop
5
which, in turn, operates to latch the clock enabling signal fed from a previous stage using the clock signal and to output it through its output terminal Q.
FIG. 15
is a timing chart showing normal operations of the conventional gated clock type logic circuit shown in
FIG. 14
while the clock supplying line picks up no spike noise. In
FIG. 15
, a “signal waveform at a terminal C” represents the signal waveform occurring at the clock input terminal C of the D-type flip flop
1
.
Referring to
FIG. 15
, when the clock enabling signal outputted from the D-type flip flop
5
is inactive (or high), the clock signal is masked in the gate circuit, while, when the clock signal is active (or low), the clock passes through the gate circuit
2
and is outputted from the gate circuit
2
, when the D-type flip flop
1
operates to latch a portion {circle around (1)} of the data input DATA (
1
) by a rising edge and to output it as a data output DATA (
0
).
FIG. 16
is a timing chart showing an example in which a fall of the clock enabling signal lags behind a fall of the clock signal, causing the occurrence of the spike noise at the clock input terminal C of the D-type flip flop
1
and resulting in a malfunction in the circuit. As shown in
FIG. 16
, while the clock enabling signal is active (or low), a portion {circle around (2)} of the data input DATA (
1
) is latched by a rising edge of the clock signal passing through the gate circuit
2
at the D-flip flop
1
and, since the rise of the clock enabling signal lags behind the fall of the clock signal, by the signal synchronizing to the rising edge of the clock enabling signal, a portion {circle around (3)} of the data input DATA (
1
) is latched at the D-type flip flop
1
and is outputted as data output DATA (
0
).
The conventional gated clock type logic circuit, however, presents problems in that, if the rise of the clock enabling signal lags behind the fall of the clock, since the spike noise causing the malfunction in the circuit occurs, in a high speed circuit having a short clock period or in a system providing a poor clock duty cycle, its use is limited in range of application.
FIG. 17
is a timing chart showing an example in which, because a delay of the clock signal occurs in the clock supplying line connected to the gate circuit, the fall of the clock enabling signal leads the rise of the clock, thus causing the occurrence of the spike noise at the clock input terminal C and resulting in the malfunction in the logic circuit. That is, in this case, while the clock enabling signal is active, by the rising edge of the clock passing through the gated circuit
2
, a portion {circle around (2)} of the data input DATA (
1
) is latched at the D-type flip flop and then by the signal synchronizing to the rising edge of the clock enabling signal, a portion {circle around (3)} of the data input DATA (
1
) is latched at the D-type flip flop
1
.
As described above, in the conventional gated clock type logic circuit, if the spike noise occurs in the clock supplying line of the D-type flip flop, data stored in the D-type flip flop is read and, at a same time, new data is captured, resulting in changes of levels at the flip flop due to influence of the spike noise, causing the malfunction in the logic circuit. Since an increase in time required for designing of the signal timing is proportional to an increase in a count of gated clock supplying lines used in a device, use of the gated clock type logic circuits tends to generally be minimized especially in a case of highly integrated circuits such as LSIs. This means that there is a relation of a trade-off between lowered power consumption in a circuit and ease in designing and time period required for designing, thus making it impossible to satisfactorily lower power consumption in the logic circuit.
Highly integrated circuits such as LSIs are designed in such a general manner that descriptions of functions and their verification are performed by using a Hardware Description Language and a gate circuit of such LSIs is synthesized based on hardware description by using a logic synthesizing tool. However, generally, most of the logic synthesizing tools are provided assuming that they would be used for a clock one phase synchronizing circuit and not for gated clock circuits and, therefore, if an existing synthesizing tool is to be employed for conventional gated clock circuits, a special way of writing is required to describe functions or only limited synthesizing tools can be used since the conventional gated clock circuit lacks in versatility in terms of ways of descriptions and designing environments, the logic circuit cannot be designed by using the existing logic synthesizing tool.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide a gated clock type logic circuit provided with a gate in its clock supplying line in which timing design can be made simple and a period of time required for designing can be shortened.
It is another object of the present invention to provide the gated clock type logic circuit which can be designed by using an existing logic synthesizing tool.
According to a first aspect of the present invention, there is provided a logic circuit including:
a gate circuit operating to allow a clock signal inputted in accordance with a level of a clock enable signal to be passed or to be masked;
a latch circuit to a clock input terminal of which an output from the gate circuit to control a latch timing for receiving data is fed;
a selector circuit into which input data and an output of the latch circuit operates to output either of the input data or the output from the latch circuit by using a data enabling signal as a selecting signal; and
whereby an output from the selector circuit is fed

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