Low-power consumption semiconductor memory device

Static information storage and retrieval – Interconnection arrangements

Reexamination Certificate

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C365S230030

Reexamination Certificate

active

06980454

ABSTRACT:
A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

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