Low-power consumption semiconductor memory device

Details Low-power consumption semiconductor memory device Low-power consumption semiconductor memory device

2003-05-14

2004-10-12

Nguyen, Viet Q. (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S226000, C365S227000, C365S189090, C365S190000, C365S202000, C365S189080

Reexamination Certificate

active

06804164

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and particularly to a dynamic semiconductor memory device with information stored in a capacitor. More particularly, the present invention relates to a dynamic semiconductor memory device suitable for integration into a system LSI (large scale integrated circuit) and operating under a low power supply voltage.
2. Description of the Background Art
A dynamic random access memory (DRAM) is generally used in order to implement a mass storage memory in a system LSI with a memory and a logic integrated therein. The DRAM includes memory cells each formed of a single capacitor and a single transistor, and therefore, the memory cell occupies a small area. Moreover, the cost per bit is inexpensive. As a result, the DRAM can implement a mass storage memory with a small occupying area.
FIG. 27
is a diagram schematically showing the structure of a main part of a conventional DRAM.
FIG. 27
shows memory cells MC
0
and MC
1
arranged in two rows and one column in a memory cell array. Bit lines BL and /BL are provided for the memory cell column, and a word line WL (WL
0
, WL
1
) are provided for each memory cell row. In
FIG. 27
, memory cell MC
0
is located at an intersection of bit line BL and word line WL
0
, whereas memory cell MC
1
is located at an intersection of bit line /BL and word line WL
1
.
Each of memory cells MC
0
, MC
1
includes a capacitor Cs for storing information, and an accessing MOS transistor (insulated-gate field effect transistor) MT. Each access transistor MT is connected through a capacitor contact to an associated memory cell capacitor Cs, and also connected through a bit line contact to a corresponding bit line BL or /BL. An electrode node of each capacitor Cs connected to the capacitor contact is referred to as a storage node SN (SN
0
, SN
1
). Charges according to the stored data are accumulated in storage node SN. A cell-plate voltage Vcp (=Vccs/2) is applied to the other electrode node (cell-plate electrode node) of each memory cell capacitor Cs.
Memory cells MC
0
and MC
1
store information by charges accumulated in the respective storage nodes SN
0
and SN
1
. Usually, word lines WL
0
and WL
1
receive a high voltage Vpp of about 3.6 V, higher than a sense power supply voltage, when selected. Such high voltage Vpp is applied in order to write high-level data of a sufficiently high voltage level (sense power supply voltage) to storage nodes SN
0
and SN
1
without a threshold-voltage loss across the corresponding access transistors MT. Bit lines BL and /BL have a voltage amplitude of about 2.0 V (=Vccs). The state in which data at a voltage Vccs level is stored in storage node SN
0
or SN
1
is referred to as high-level data storage, whereas the state in which data at a ground-voltage GND level is stored in storage node SN
0
or SN
1
is referred to as low-level data storage.
A circuit for reading the data stored in memory cell MC
0
or MC
1
is called a sense amplifier circuit. The sense amplifier circuit includes a sense amplifier
900
that is activated to differentially amplify a voltage on bit lines BL and /BL, and sense activation transistors PQ
3
and NQ
3
responsive to respective sense amplifier activation signals /SOP and SON for transmitting a power supply voltage Vccs and ground voltage GND to internal power source nodes of sense amplifier
900
, respectively. Sense amplifier
900
includes a P-channel MOS transistor PQ
1
connected between a first internal power source node and bit line BL and having its gate connected to bit line /BL, a P-channel MOS transistor PQ
2
connected between the first internal power source node and bit line /BL and having its gate connected to bit line BL, an N-channel MOS transistor NQ
1
connected between bit line BL and a second internal power source node and having its gate connected to bit line /BL, and an N-channel MOS transistor NQ
2
connected between bit line /BL and the second internal power source node and having its gate connected to bit line BL. Sense amplifier activation transistor PQ
3
formed by a P-channel MOS transistor is rendered conductive in response to activation of sense amplifier activation signal /SOP for transmitting sense power supply voltage Vccs to the first internal power source node. Sense amplifier activation transistor NQ
3
formed by an N-channel MOS transistor is rendered conductive in response to activation of sense amplifier activation signal SON for transmitting ground voltage GND to the second internal power source node.
A bit-line precharging/equalizing circuit
902
is further provided in order to precharge and equalize bit lines BL and /BL to an intermediate voltage in the standby state. Bit-line precharging/equalizing circuit
902
includes N-channel MOS transistors NQ
4
and NQ
5
rendered conductive in response to activation of a bit-line equalization instruction signal BLEQ for transmitting a bit-line precharge voltage VBL (=Vccs/2) to bit lines BL and /BL, and an N-channel MOS transistor NQ
6
rendered conductive in response to activation of bit-line equalization instruction signal BLEQ for electrically short-circuiting bit lines BL and /BL.
Bit-line precharging/equalizing circuit
902
is used to precharge and equalize bit lines BL and /BL to the intermediate voltage level during the standby state. As a result, bit lines BL and /BL have a reduced amplitude in sensing operation, whereby high-speed sensing as well as reduction in a sense current are achieved. Now, the operation of reading the data in the memory cells shown in
FIG. 27
is briefly described with reference to
FIGS. 28 and 29
.
Referring first to
FIG. 28
, a sensing operation for reading high-level data (H data) stored in storage node SN
0
of memory cell MC
0
is described. In the standby state, bit lines BL and /BL are precharged and equalized to the intermediate voltage Vccs/2 level by bit-line precharging/equalizing circuit
902
. Sense amplifier activation signal /SOP is at the sense power supply voltage Vccs level, whereas sense amplifier activation signal SON is at the ground voltage GND level. Accordingly, sense amplifier activation transistors PQ
3
and NQ
3
are both in the OFF state.
When an active cycle is started, bit-line equalization instruction signal BLEQ first becomes inactive, whereby bit-line precharging/equalizing circuit
902
is deactivated. Thus, bit lines BL and /BL are brought into a floating state at the intermediate voltage Vccs/2 level.
Then, a row selecting operation is performed according to an address signal not shown, and word line WL
0
is selected. The selected word line WL
0
is driven to the high voltage Vpp level that is higher than sense power supply voltage Vccs. Access transistor MT of memory cell MC
0
is rendered conductive in response to the voltage rise on word line WL
0
. As a result, storage node SN
0
is coupled to bit line BL, and charges accumulated in storage node SN
0
are transmitted onto bit line BL. Since H data (high level data) is stored in storage node SN
0
, bit line BL voltage is raised by a reading voltage &Dgr;V from precharge voltage Vccs/2 (the voltage levels on bit line BL and storage node SN
0
become equal to each other). However, since there is no memory cell arranged at the intersection of bit line /BL and word line WL
0
, bit line /BL is maintained at the precharge-voltage Vccs/2 level.
When the voltage difference between bit lines BL and /BL, i.e., the reading voltage &Dgr;V, is sufficiently developed, sense amplifier activation signals SON and /SOP are activated. As a result, sense amplifier activation transistors PQ
3
and NQ
3
are rendered conductive, and sense amplifier
900
starts the sensing operation. During the sensing operation, sense amplifier
900
differentially amplifies the read voltage &Dgr;V on bit lines BL and /BL, thereby driving bit line BL to the sense power supply voltage Vccs level and bit line /BL to the ground voltage level.
Referring now to
FIG. 29
, a sen

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