Low-power-consumption liquid crystal display driver

Details Low-power-consumption liquid crystal display driver Low-power-consumption liquid crystal display driver

1999-01-04

2001-10-09

Saras, Steven (Department: 2775)

Computer graphics processing and selective visual display system

Plural physical display element control system

Display elements arranged in matrix

C345S099000

Reexamination Certificate

active

06300930

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to a liquid crystal display driver and, more particularly, to a liquid crystal display driver having a common line driver for sequentially driving common signal lines of a liquid crystal display panel.
DESCRIPTION OF THE RELATED ART
A typical example of the liquid crystal display driver is illustrated in
FIG. 1
of the drawing. The prior art liquid crystal display driver
1
is associated with a liquid crystal display panel
2
. The liquid crystal display panel
2
includes pixels P00, P01, . . . , P0n, P10, P11, . . . , P1n, . . . , Pm0, Pm1, . . . and Pmn arranged in matrix, common signal lines C
0
, C
1
, . . . , Cm respectively associated with the rows of pixels P00-P0n, P10-P1n, . . . , Pm0-Pmn and segment signal lines S
0
, S
1
, . . . , Sn respectively associated with the columns of pixels P00-Pm0, P01-Pm1, . . . , P0n−Pmn. Though not shown in
FIG. 1
, a thin film transistor and a piece of liquid crystal sandwiched between a pixel electrode and a part of a common electrode form in combination each of the pixels P00 to Pmn. The common signal line CO, C
1
. . . or Cm is connected to the gate electrodes of the thin film transistors forming the associated row, and is sometimes called as “gate line”. On the other hand, the segment signal line S
0
, S
1
, . . . or Sn is connected to the source nodes of the thin film transistors forming the associated column, and is sometimes called as “source line”.
The prior art liquid crystal display driver
1
includes a common line driver
3
, a segment line driver
4
and a control circuit
5
. The common line driver
3
is connected to the common signal lines C
0
to Cm, and sequentially supplies a common signal to the common signal lines C
0
to Cm. On the other hand, the segment line driver
4
is connected to the segment signal lines S
0
to Sn, and supplies segment signals representative of a part of image to be produced on a row of pixels to the segment signal lines S
0
to Sn in synchronism with the common signal. While the common line driver
3
is supplying the common signal from the common signal line C
0
to the common signal line Cm, the segment signals produces the image on the pixel matrix P00 to Pmn, and the time period for producing the image is called as “frame”.
The control circuit
5
is connected to the common line driver
3
and the segment line driver
4
, and controls the image producing operation on the pixel matrix P00 to Pmn. The control circuit
5
supplies potential signals V
1
/V
2
and a selecting signal SEL to the common line driver
3
, and the common line driver
3
generates the common signal Sc
0
/Sc
1
/ . . . /Scm at different timings. An image carrying signal IMG representative of the image is supplied to the control circuit
5
, and the control circuit
5
instructs the segment line driver
4
to regulate each of the segment signals to an appropriate potential level.
FIG. 2
illustrates the common line driver
3
. The common line driver
3
comprises analog switching units SW
0
, SW
1
, . . . and SWm, and each of the analog switching units SW
0
to SWm is implemented by a pair of analog switches ALG
1
/ALG
2
. The potential signal V
1
and the other potential signal V
2
are supplied to the analog switches ALG
1
and the other analog switches ALG
2
, respectively. The pairs of analog switches ALG
1
/ALG
2
are connected to the common signal lines C
0
, C
1
, . . . and Cm, respectively, and are controlled with the selecting signal SEL. The selecting signal SEL comprises selecting sub-signals SEL
0
, SEL
1
, . . . and SELm, and the selecting sub-signals SEL
0
to SELm are respectively supplied to the analog switching units SW
0
to SWm, respectively. The control circuit
5
sequentially changes the selecting sub-signals SEL
0
to SELm to active high level. The selecting sub-signals SEL
0
to SELm are directly supplied to the analog switches ALG
1
, and the other analog switches ALG
2
are supplied with the complementary signals thereof internally generated. For this reason, the analog switch ALG
1
and the associated analog switch ALG
2
complementarily turn on and off, and supplies the common signal Sc
0
/Sc
1
/ . . . /Scm to the associated common signal line C
0
/C
1
/ . . . /Cm.
The prior art common line driver
3
behaves as illustrated in FIG.
3
. Frame F
1
is continued from time t0 to time t3, and frame F
2
is continued from time t3 to time t6. The control circuit
5
regulates the potential signal V
1
and the other potential signal V
2
to potential level Va and potential level Vc in the frame F
1
, and sequentially changes the selecting sub-signals SEL
0
, SEL
1
, . . . and SELm to active high level at time t0, time t1, . . . and time t2. While the control circuit
5
is maintaining one of the selecting sub-signals SEL
0
/SEL
1
/ . . . /SELm at the active high level, the other selecting sub-signals are maintained at inactive low level.
The selecting sub-signals SEL
0
, SEL
1
, . . . and SELm of the active high level cause the associated analog switches ALG
1
to sequentially turn on, and the analog switching units SW
0
, SW
1
, . . . and SWm supply the common signal Sc
0
/Sc
1
/ . . . /Scm of the potential level Va to the associated common signal lines C
0
, C
1
, . . . and Cm at time t0, time t1, . . . and time t2. When the selecting sub-signals SEL
0
/SEL
1
/ . . . SELm stay at the inactive low level, the analog switches ALG
1
is turned off, and the associated analog switches ALG
2
are turned on. Thus, only one common signal line C
0
, C
1
, . . . or Cm is changed to the potential level Va, and the other common signal lines are maintained at the potential level Vc.
The control circuit
5
regulates the potential signal V
1
and the other potential signal V
2
to potential level Vd and potential level Vb in the next frame F
2
, and sequentially changes the selecting sub-signals SEL
0
, SEL
1
, . . . and SELm to the active level at time t3, time t4, . . . and time t5.
The selecting sub-signals SEL
0
, SEL
1
, . . . and SELm are changed to the active high level at time t3, time t4, . . . and time t5, and cause the analog switches ALG
1
to sequentially turn on. However, the other selecting sub-signals are maintained at the inactive low level, and the associated analog switches ALG
2
are turned on. For this reason, the common signal Sc
0
/Sc
1
. . . /Scm changes the associated common signal line C
0
/C
1
/ . . . /Cm to the potential level Vd at time t3, time t4, . . . and time t5, and the other common signal lines are maintained at the potential level Vb.
In this way, the prior art common line driver
3
alternates the common signal Sc
0
to Scm between the potential range Va-Vc and the potential range Vd-Vb. As a result, the common signal Sc
0
-Scm changes the active level between Va and Vd and the inactive level between Vc and Vb.
A problem is encountered in the prior art liquid crystal display driver
3
in electric power consumption.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a liquid crystal display driver, which consumes a small amount of electric power.
The present inventor contemplated the problem, and noticed that each of the common signal lines C
0
/C
1
/ . . . Cm was independently charged and discharged. The control circuit
5
was expected to swing the common signal lines C
0
/C
1
/ . . . Cm between the potential level Va/Vd and the potential level Vc/Vb, and consumed a large amount of electric power. The present inventor concluded that the common line driver
3
had to reuse the current discharged from the common signal line changed from the selected state to the non-selected state.
In accordance with one aspect of the present invention, there is provided a liquid crystal display driver associated with a liquid crystal display panel having a plurality of selecting lines for selectively activating pixels and a plurality of data lines for producing a piece of image on the activated pixels in each frame and comprising a control circuit sequentially changing preliminary s

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