Low power consumption integrated circuit for a combined timepiec

Details Low power consumption integrated circuit for a combined timepiec Low power consumption integrated circuit for a combined timepiec

1979-04-26

1981-05-12

Smith, Jerry

Boots, shoes, and leggings

364705, G06F 1502, G04B 4700

Patent

active

042675774

ABSTRACT:
An integrated circuit device having a combined time-keeping mode and calculator mode comprises a generator stage for generating basic clock signals and system clock signals, a processor stage responsive to a supply of the system clock signals for executing arithmetic operations required for the timekeeping mode and the calculator mode key input members for introducing information into the processor stage as key input signals, and a clock control for controlling the supply of the system clock signals. The processor stage is adapted to develop a command signal to indicate the completion of the arithmetic operations. The clock control is responsive to the rising and trailing edges of the key input signals for enabling the supply of the system clock signals. The generation of the command signal causes the clock control to prevent the system clock signals from being fed to the processor stage.

REFERENCES:
patent: 3941989 (1976-03-01), McLaughlin et al.
patent: 3955355 (1976-05-01), Luce
patent: 4093992 (1978-06-01), Kawamura et al.

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