Low power consumption circuit and method of operation for implem

Details Low power consumption circuit and method of operation for implem Low power consumption circuit and method of operation for implem

1995-07-03

1997-10-28

Elmore, Reba I.

Boots, shoes, and leggings

377 54, 377 69, 377 73, 377 74, 395775, G06F 700, G06F 1500, G11C 1900

Patent

active

056823401

ABSTRACT:
The present invention describes a circuit (10) and associated method of operation for implementing bit reversals and shifts of an input data. The circuit (10) includes a plurality of input lines (12), a plurality of output lines (14), a plurality of shifting transistors (16), a plurality of bit reversal transistors (20), control lines (18) and (22) for each, and a controller (24). The plurality of shifting transistors (16) operably couple the input lines (12) to the output lines (14) such that the controller (24) may selectively operate the shifting transistors (22) to produce shifted outputs of the input data D.sub.0 through D.sub.3 on the output lines (14). The controller (24) selectively operates the bit reversal transistors (20) to produce a bit reversed representation of the input data on the output lines (14). Precharge circuit (30) precharges the output lines (14) so that they may be statically driven. The circuit (10) may include multiplexors (25), (26), and (27) to enable arithmetic shifts.

REFERENCES:
patent: 3768077 (1973-10-01), Nier et al.
patent: 4782457 (1988-11-01), Cline
patent: 4811369 (1989-03-01), Barnard et al.
patent: 4829460 (1989-05-01), Ito
patent: 4984189 (1991-01-01), Neki
patent: 5132898 (1992-07-01), Sakamura et al.
patent: 5265259 (1993-11-01), Satou et al.
patent: 5297070 (1994-03-01), Hua et al.

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