Low power consumption analog-to-digital converter

Details Low power consumption analog-to-digital converter Low power consumption analog-to-digital converter

2009-03-30

2010-10-19

JeanPierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S161000

Reexamination Certificate

active

07817071

ABSTRACT:
A low power consumption analog-to-digital converter (ADC) is provided. The switched capacitor circuit and the operational amplifier of the pipelined stage within the present low power consumption ADC are designed to close loop, and the operational amplifier is operated at the incomplete settling of the linear settling, namely, the operational amplifier is not operated at the slew state. Therefore, the pipelined stage would not produce signal dependent distortion, such that the gain error produced by the operational amplifier could be seen as a constant gain error.

REFERENCES:
patent: 7064700 (2006-06-01), Garrity et al.
patent: 7106240 (2006-09-01), Cringean
patent: 7733261 (2010-06-01), Bhakta et al.
B. Murmann et al., “A 12-b 75-MS/s pipelined ADC using open-loop residue amplification”, IEEE J. Solid-State Circuits, vol. 38, No. 12, pp. 2040-2050, Dec. 2003.
E. Iroaga et al., “A 12-bit 75-MS/s pipelined ADC using incomplete Settling ” IEEE J. Solid-State Circuits, vol. 42, No. 4, pp. 748-765, Apr. 2007.
T. Sepke et al., “ Comparator Based switched capacitor circuits for scaled CMOS Technologies” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, Feb. 2006, pp. 220-222.

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