Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons
Patent
1982-12-28
1986-01-07
Miller, Stanley D.
Electrical transmission or interconnection systems
Nonlinear reactor systems
Parametrons
307443, 307453, 307481, 307482, 307463, 307279, H03K 19096, H03K 1706
Patent
active
045635986
ABSTRACT:
The present invention is directed to a decoder circuit for a semiconductor memory device including a logic circuit for receiving an address signal as an input thereto and selecting an address in response thereto and a load in the logic circuit. The load comprises a pair of transistors connected in parallel, wherein one of the pair of transistors turns ON for a specified period in synchronization with the address signal, and the other of the pair of transistors turns ON when the logic circuit is in a selected condition and turns OFF when the logic circuit is in a non-selected condition.
REFERENCES:
patent: 4086500 (1978-04-01), Suzuki et al.
patent: 4099265 (1978-07-01), Abe
patent: 4185320 (1980-01-01), Takemae et al.
patent: 4398102 (1983-08-01), Stewart
patent: 4471240 (1984-09-01), Novosel
IEEE International Solid-State Circuits Conference, vol. 20, No. 20, Feb. 1977, pp. 14-15, New York, USA.
T. R. O'Connell et al., "A4K Static Clocked and Nonclocked RAM Design".
Patent Abstract of Japan, vol. 5, No. 134(P-77) (806), Aug. 26, 1981 & JP-1-56 71881 (Fujitsu K.K.) 15-06-1981.
Fujitsu Limited
Hudspeth D. R.
Miller Stanley D.
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