Low-power column parallel ADC in CMOS image sensors

Details Low-power column parallel ADC in CMOS image sensors Low-power column parallel ADC in CMOS image sensors

1998-11-04

2000-10-24

Young, Brian

Coded data generation or conversion

Analog to or from digital conversion

Analog to digital conversion

341170, 341155, H03M 156

Patent

active

061374326

ABSTRACT:
A low-power column parallel ADC architecture for image sensors that reduces the power consumption by reducing the number of switchings of a comparator to digitize a row of pixel data. Two ramp reference signals are provided in accordance with the principles of this invention. A first ramp signal is provided to each comparator that is clocked with an associated first clock signal. In each column comparator, the first ramp signal is compared to the pixel data using clock1, wherein clock1 corresponds to N multiple of a second clock signal (clock2), with N>1. Only when the column comparator detects a first crossover with the first ramp signal, then the comparator switches at every clock cycle of the second clock, clock2, to compare and detect a second crossover point with the second reference signal. This arrangement can greatly reduce the number of switchings required to digitize a row of pixel data, thereby resulting in significant power saving.

REFERENCES:
patent: 4851839 (1989-07-01), Reinke
patent: 5321404 (1994-06-01), Mallinson et al.
patent: 5461425 (1995-10-01), Fowler et al.
patent: 5613156 (1997-03-01), Katayama
B. Pain and E.R. Fossum, Approaches and Analysis For On-Focal-Plane Analog-to-Digital Conversion, SPIE, 1994, pp. 208-218, vol. 2226, Infrared Readout Electronics II.

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