Low-power column decode circuit

Details Low-power column decode circuit Low-power column decode circuit

1999-09-03

2000-07-11

Nguyen, Viet Q.

Static information storage and retrieval

Addressing

Sync/clocking

36523003, 36523006, 36523001, 36523008, G11C 800

Patent

active

06088293&

ABSTRACT:
A memory circuit is designed with a memory array (113, 115, 117, 119) having a plurality of banks. Each bank is addressable in response to a bank address signal (102), and each bank arranged in rows and columns of memory cells. Each of plural data leads (122) corresponds to a bank. Each data lead is selectively connected to a column of memory cells by a respective select transistor. A first decode circuit (501) has at least one input and one output terminal. The output terminal (525) is coupled to a control gate of at least one of the select transistors. Each of a plurality of second decode circuits (231) corresponds to a respective bank. Each second decode circuit has a memory element (423, 425, 428)), a plurality of input terminals and at least one output terminal. One second decode circuit input terminal (227) is coupled to receive a first address signal. Another second decode circuit input terminal (229) is coupled to receive the bank address signal. The second decode circuit output terminal coupled to the input terminal of the first decode circuit. The second decode circuit is arranged to store the first address signal in the memory element in response to the bank address signal.

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patent: 5970016 (1999-10-01), Ohsawa
patent: 5996043 (1999-11-01), Manning
patent: 6026045 (2000-02-01), Son

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