Low power CMOS line driver with dynamic biasing

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Slope control of leading or trailing edge of rectangular or...

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327108, 327112, 326 82, 326 86, H03K 309

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active

059260491

ABSTRACT:
A low power line driver uses a dynamic biasing scheme together with single ended architecture to achieve low power, fast speed and high return loss. The line driver includes a first and second operation amplifier each having an output port for generating an output pulse signal having a rising and falling edge. The load is coupled to the first and second output port by a transformer. A first and second digital control circuit is coupled to the first and second operational amplifiers to control the operational amplifiers. The first and second operational amplifiers further include a pulse circuit for generating the output pulse signal and a selectable current source having a first mode for injecting a high current to the pulse circuit to provide a high slew rate for the rising edge of the output pulse signal and a second mode for injecting a second current to the pulse circuit during the generation of the remaining portion of the output pulse signal. An output impedance control element is provided for providing a low output impedance during a second phase. A digital control circuit is provided for providing control signals to the pulse circuit and the selectable current source for controlling the timing and generation of the output pulse signal. Finally, a processes compensation circuit is provided for reducing dynamic current amplitude variation for the circuit elements.

REFERENCES:
patent: 5410262 (1995-04-01), Kang
patent: 5471171 (1995-11-01), Itakura et al.
patent: 5512859 (1996-04-01), Moraveji
patent: 5729178 (1998-03-01), Park et al.
patent: 5739715 (1998-04-01), Rawson

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